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* [X86] Improve the diagnostic for larger than 4-bit immediate for ↵Craig Topper2019-08-101-2/+2
| | | | | | vpermil2pd/ps. Only allow MCConstantExprs. llvm-svn: 368505
* [X86] Limit vpermil2pd/vpermil2ps immediates to 4 bits in the assembly parser.Craig Topper2019-08-071-0/+4
| | | | | | | | | | The upper 4 bits of the immediate byte are used to encode a register. We need to limit the explicit immediate to fit in the remaining 4 bits. Fixes PR42899. llvm-svn: 368123
* [X86] Add support for {vex2}, {vex3}, and {evex} to the assembler to match ↵Craig Topper2019-04-091-0/+12
| | | | | | | | | | | | | | | | gas. Use {evex} to improve the one our 32-bit AVX512 tests. These can be used to force the encoding used for instructions. {vex2} will fail if the instruction is not VEX encoded, but otherwise won't do anything since we prefer vex2 when possible. Might need to skip use of the _REV MOV instructions for this too, but I haven't done that yet. {vex3} will force the instruction to use the 3 byte VEX encoding or fail if there is no VEX form. {evex} will force the instruction to use the EVEX version or fail if there is no EVEX version. Differential Revision: https://reviews.llvm.org/D59266 llvm-svn: 358029
* [X86] Re-disable cmpxchg16b for 32-bit mode assembly parsing.Craig Topper2019-03-191-0/+3
| | | | | | This was broken recently when I factored the 64 bit mode check into hasCmpxchg16 without thinking about the AssemblerPredicate. llvm-svn: 356531
* [X86] Disable CQTO and CLTQ instructions in the assembly parser outside ↵Craig Topper2019-03-181-0/+6
| | | | | | 64-bit mode. llvm-svn: 356419
* [MC][X86] Add test case for invalid use of "(%dx)" operand.Nirav Dave2019-01-141-0/+4
| | | | llvm-svn: 351094
* [X86] Fix incomplete handling of register-assigned variables in parsing.Nirav Dave2019-01-111-0/+36
| | | | | | | | | | | | | | Teach x86 assembly operand parsing to distinguish between assembler variable assigned to named registers and those assigned to immediate values. Reviewers: rnk, nickdesaulniers, void Subscribers: hiraditya, jyknight, llvm-commits Differential Revision: https://reviews.llvm.org/D56287 llvm-svn: 350966
* [X86][Assembler] Allow %eip as a register in 32-bit mode for .cfi directives.Craig Topper2018-09-061-2/+2
| | | | | | | | | | This basically reverts a change made in r336217, but improves the text of the error message for not allowing IP-relative addressing in 32-bit mode. Fixes PR38826. Patch by Iain Sandoe. llvm-svn: 341512
* [X86][AsmParser] Don't consider %eip as a valid register outside of 32-bit mode.Craig Topper2018-07-031-2/+2
| | | | | | | | This might make the error message added in r335668 unneeded, but I'm not sure yet. The check for RIP is technically unnecessary since RIP is in GR64, but that fact is kind of surprising so be explicit. llvm-svn: 336217
* [X86][AsmParser] Improve base/index register checks.Craig Topper2018-06-231-0/+16
| | | | | | | | | -Ensure EIP isn't used with an index reigster. -Ensure EIP isn't used as index register. -Ensure base register isn't a vector register. -Ensure eiz/riz usage matches the size of their base register. llvm-svn: 335412
* [X86] Don't accept (%si,%bp) 16-bit address expressions.Craig Topper2018-06-221-0/+13
| | | | | | | | | | The second register is the index register and should only be %si or %di if used with a base register. And in that case the base register should be %bp or %bx. This makes us compatible with gas. We do still need to support both orders with Intel syntax which uses [bp+si] and [si+bp] llvm-svn: 335384
* [X86] Don't allow ESP/RSP to be used as an index register in assembly.Craig Topper2018-06-221-0/+8
| | | | | | Fixes PR37892 llvm-svn: 335370
* [X86] Add a Requires<[In64BitMode]> to FARJMP64Craig Topper2018-04-301-0/+3
| | | | | | Otherwise we can try to assemble it in 32-bit mode and throw an assert in the encoder. llvm-svn: 331161
* [X86] Remove checks for FeatureAVX512 from the X86 assembly parser. Remove ↵Craig Topper2018-02-021-4/+0
| | | | | | | | | | | | | | | | | | | | | mcpu/mattr from assembly test command lines. Summary: We should always be able to accept AVX512 registers and instructions in llvm-mc. The only subtarget mode that should be checked is 16-bit vs 32-bit vs 64-bit mode. I've also removed all the mattr/mcpu lines from test RUN lines to be consistent with this. Most were due to AVX512, but a few were for other features. Fixes PR36202 Reviewers: RKSimon, echristo, bkramer Reviewed By: echristo Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D42824 llvm-svn: 324106
* [X86] Don't randomly encode %rip where illegalDouglas Katzman2016-10-051-0/+8
| | | | | | Differential Revision: https://reviews.llvm.org/D25112 llvm-svn: 283326
* [X86] Don't allow DR8-DR15 to be assembled in 32-bit mode. Add missing test ↵Craig Topper2016-08-271-0/+6
| | | | | | for CR8-CR15. llvm-svn: 279921
* [X86] Add test cases for r261977 and fix a grammatical error.Craig Topper2016-02-261-0/+4
| | | | llvm-svn: 261983
* [X86] Add proper 64-bit mode checks to jrcxz and jcxz.Craig Topper2015-07-041-0/+6
| | | | llvm-svn: 241381
* [x86] Add assembly parser bounds checking to the immediate value for ↵Craig Topper2015-01-211-0/+8
| | | | | | cmpss/cmpsd/cmpps/cmppd. llvm-svn: 226642
* X86 MC: Reject invalid segment registers before a memory operand colonReid Kleckner2014-07-311-0/+4
| | | | | | Previously we would execute unreachable during object emission. llvm-svn: 214456
* [x86] Make AsmParser validate registers for memory operands a bit betterDavid Woodhouse2014-01-081-1/+16
| | | | | | | | | | | | We can't do a perfect job here. We *have* to allow (%dx) even in 64-bit mode, for example, because it might be used for an unofficial form of the in/out instructions. We actually want to do a better job of validation *later*. Perhaps *instead* of doing it where we are at the moment. But for now, doing what validation we *can* do in the place that the code already has its validation, is an improvement. llvm-svn: 198760
* [ms-inline asm] Fix a crasher when we fail on a direct match.Chad Rosier2013-05-101-0/+3
| | | | | | | | | | | | | | | | | | The issue was that the MatchingInlineAsm and VariantID args to the MatchInstructionImpl function weren't being set properly. Specifically, when parsing intel syntax, the parser thought it was parsing inline assembly in the at&t dialect; that will never be the case. The crash was caused when the emitter tried to emit the instruction, but the operands weren't set. When parsing inline assembly we only set the opcode, not the operands, which is used to lookup the instruction descriptor. rdar://13854391 and PR15945 Also, this commit reverts r176036. Now that we're correctly parsing the intel syntax the pushad/popad don't match properly. I've reimplemented that fix using a MnemonicAlias. llvm-svn: 181620
* X86: Better diagnostics for 32-bit vs. 64-bit mode mismatches.Jim Grosbach2012-11-141-1/+1
| | | | | | | | | | When an instruction as written requires 32-bit mode and we're assembling in 64-bit mode, or vice-versa, issue a more specific diagnostic about what's wrong. rdar://12700702 llvm-svn: 167937
* Added a missing error check for X86 assembly with mismatched base and indexKevin Enderby2012-03-121-0/+4
| | | | | | registers not both being 64-bit or both being 32-bit registers. llvm-svn: 152580
* Add the missing call to Error when a bad X86 scale expression is parsed.Kevin Enderby2012-03-091-0/+4
| | | | llvm-svn: 152443
* Change the sysexit mnemonic (and sysexitl) to never have the REX.W prefix andKevin Enderby2011-10-271-0/+2
| | | | | | | not depend on In32BitMode. Use the sysexitq mnemonic for the version with the REX.W prefix and only allow it only In64BitMode. rdar://9738584 llvm-svn: 143112
* Enhance llvm::SourceMgr to support diagnostic ranges, the same way clang ↵Chris Lattner2011-10-161-0/+3
| | | | | | | | | | | | | | | does. Enhance the X86 asmparser to produce ranges in the one case that was annoying me, for example: test.s:10:15: error: invalid operand for instruction movl 0(%rax), 0(%edx) ^~~~~~~ It should be straight-forward to enhance filecheck, tblgen, and/or the .ll parser to use ranges where appropriate if someone is interested. llvm-svn: 142106
* Finish supporting cpp #file/line comments in assembler for error messages. SoKevin Enderby2011-10-121-0/+5
| | | | | | | | for cpp pre-processed assembly we give correct filename and line numbers when reporting errors in assembly files when using clang and -integrated-as on .s files. rdar://8998895 llvm-svn: 141814
* Emit an error is asm parser parsed X86_64 only registers, e.g. %rax, %sil.Evan Cheng2011-07-271-2/+9
| | | | | | | | | This can happen in cases where TableGen generated asm matcher cannot check whether a register operand is in the right register class. e.g. mem operands. rdar://8204588 llvm-svn: 136292
* move X86 subdir up a levelChris Lattner2010-10-011-0/+5
llvm-svn: 115292
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