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* [X86] Remove checks for FeatureAVX512 from the X86 assembly parser. Remove ↵Craig Topper2018-02-021-1/+1
| | | | | | | | | | | | | | | | | | | | | mcpu/mattr from assembly test command lines. Summary: We should always be able to accept AVX512 registers and instructions in llvm-mc. The only subtarget mode that should be checked is 16-bit vs 32-bit vs 64-bit mode. I've also removed all the mattr/mcpu lines from test RUN lines to be consistent with this. Most were due to AVX512, but a few were for other features. Fixes PR36202 Reviewers: RKSimon, echristo, bkramer Reviewed By: echristo Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D42824 llvm-svn: 324106
* [X86][AsmParser][AVX512] Error appropriately when K0 is tried as a write-maskCoby Tayree2017-08-131-0/+3
| | | | | | | | | K0 isn't expected as a write-mask, so provide a detailed error here, instead of the more generic one (invalid op for insn) Conforms with gas Differential Revision: https://reviews.llvm.org/D36570 llvm-svn: 310789
* [AsmParser][AVX512]Enhance OpMask/Zero/Merge syntax check rubostnessCoby Tayree2017-08-091-0/+9
Adopt a more strict approach regarding what marks should/can appear after a destination register, when operating upon an AVX512 platform. Differential Revision: https://reviews.llvm.org/D35785 llvm-svn: 310467
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