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* [X86] Remove the suffix on vcvt[u]si2ss/sd register variants in assembly ↵Craig Topper2019-05-061-76/+76
| | | | | | | | | | | | | | printing. We require d/q suffixes on the memory form of these instructions to disambiguate the memory size. We don't require it on the register forms, but need to support parsing both with and without it. Previously we always printed the d/q suffix on the register forms, but it's redundant and inconsistent with gcc and objdump. After this patch we should support the d/q for parsing, but not print it when its unneeded. llvm-svn: 360085
* [X86] Remove the _alt forms of AVX512 VPCMP instructions. Use a combination ↵Craig Topper2019-03-171-2/+2
| | | | | | | | | | of custom printing and custom parsing to achieve the same result and more Similar to the previous patch for VPCOM. Differential Revision: https://reviews.llvm.org/D59398 llvm-svn: 356344
* [X86] Move the 'vmovq.s' and similar assembly strings for EVEX vector moves ↵Craig Topper2018-06-181-124/+124
| | | | | | | | | | with reversed operands to InstAliases. The .s assembly strings allow the reversed forms to be targeted from assembly which matches gas behavior. But when printing the instructions we should print them without the .s to match other tooling like objdump. By using InstAliases we can use the normal string in the instruction and just hide it from the assembly parser. Ideally we'd add the .s versions to the legacy SSE and VEX versions as well for full compatibility with gas. Not sure how we got to state where only EVEX was supported. llvm-svn: 334920
* [TableGen] Prevent double flattening of InstAlias asm strings in the asm ↵Craig Topper2018-06-181-0/+8
| | | | | | | | | | | | matcher emitter. Unlike CodeGenInstruction, CodeGenInstAlias was flatting asm strings in its constructor. For instructions it was the users responsibility to flatten the string. AsmMatcherEmitter didn't know this and treated them the same. This caused double flattening of InstAliases. This is mostly harmless unless the desired assembly string contains curly braces. The second flattening wouldn't know to ignore these and would remove the curly braces. And for variant 1 it would remove the contents of them as well. To mitigate this, this patch makes removes the flattening from the CodeGenIntAlias constructor and modifies AsmWriterEmitter to account for the flattening not having been done. llvm-svn: 334919
* [X86] Remove checks for FeatureAVX512 from the X86 assembly parser. Remove ↵Craig Topper2018-02-021-1/+1
| | | | | | | | | | | | | | | | | | | | | mcpu/mattr from assembly test command lines. Summary: We should always be able to accept AVX512 registers and instructions in llvm-mc. The only subtarget mode that should be checked is 16-bit vs 32-bit vs 64-bit mode. I've also removed all the mattr/mcpu lines from test RUN lines to be consistent with this. Most were due to AVX512, but a few were for other features. Fixes PR36202 Reviewers: RKSimon, echristo, bkramer Reviewed By: echristo Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D42824 llvm-svn: 324106
* [X86] Remove memory forms of EVEX encoded vcvttss2si/vcvttsd2si from asm ↵Craig Topper2018-01-061-8/+8
| | | | | | | | matcher table. This is also needed to fix PR35837. llvm-svn: 321946
* [X86] Remove memory forms of EVEX encoded vcvtsd2si/vcvtss2si from the ↵Craig Topper2018-01-061-4/+4
| | | | | | | | | | assembler matcher table We should always prefer the VEX encoded version of these instructions. There is no advantage to the EVEX version. Fixes PR35837. llvm-svn: 321939
* [X86] Add vcvtsd2sil/vcvtsd2siq etc. InstAliases to the EVEX-encoded ↵Craig Topper2018-01-051-0/+64
| | | | | | | | instructions. This matches their VEX equivalents. llvm-svn: 321912
* [X86] Add InstAliases for 'vmovd' with GR64 registers to select EVEX encoded ↵Craig Topper2018-01-051-0/+8
| | | | | | | | | | instructions as well. Without this we allow "vmovd %rax, %xmm0", but not "vmovd %rax, %xmm16" This exists due to continue a silly bug where really old versions of the GNU assembler required movd instead of movq on these instructions. This compatibility hack then crept forward to avx version too, but we didn't propagate it to avx512. llvm-svn: 321903
* [AVX-512] Add more gather/scatter encoding test cases.Craig Topper2017-01-161-0/+48
| | | | llvm-svn: 292089
* [X86] [AVX512] Minor fix in encoding of scalar EVEX instructions. NFC.Michael Zuckerman2016-12-181-18/+18
| | | | | | | | | | | | Commit on behalf of Gadi Haber Removed EVEX_V512 prefix from scalar EVEX instructions since HW ignores L'L bits anyway (LIG). 4 instructions are modified. The changed encodings are validated with XED. Rviewers: delena, igorb Differential revision: https://reviews.llvm.org/D27802 llvm-svn: 290065
* [AVX-512] Add suffixless aliases for EVEX encoded ↵Craig Topper2016-11-141-0/+18
| | | | | | | | vcvtsi2ss/vcvtsi2sd/vcvtusi2ss/vcvtusi2sd. This matches the VEX behavior. Fixes another problem from PR28850. llvm-svn: 286790
* [AVX512] Add aliases for vcvttss2si{l|q}, vcvttsd2si{l|q}, vcvttss2usi{l|q}, ↵Igor Breger2016-08-031-0/+128
| | | | | | | | vcvttsd2usi{l|q} instructions. Differential Revision: http://reviews.llvm.org/D23111 llvm-svn: 277586
* AVX512: Fix scalar mem operands.Igor Breger2016-02-221-54/+54
| | | | | | Differential Revision: http://reviews.llvm.org/D17500 llvm-svn: 261520
* [AVX512] [CMPPS ][ CMPPD ] Adding full Comparison Predicate names Michael Zuckerman2016-01-251-0/+208
| | | | | | | | | | | X86AsmParser.cpp is missing full comparison predicate names for CMPPD and CMPPS Instructions. X86AsmParser.cpp defines only the short names of the Comparison predicate that you can find in the following pdf: https://software.intel.com/sites/default/files/managed/07/b7/319433-023.pdf Page 5-61 table 5-3 Differential Revision: http://reviews.llvm.org/D16518 llvm-svn: 258671
* [AVX-512] Make spacing between comma and {sae} operand consistent in asm ↵Craig Topper2016-01-111-28/+28
| | | | | | strings. llvm-svn: 257299
* [AVX512] Bring vmovq instructions names into alignment with the AVX and SSE ↵Craig Topper2015-12-281-12/+12
| | | | | | | | names. Add a missing encoding to disassembler and assembler. I believe this also fixes a case where a 64-bit memory form that is documented as being unsupported in 32-bit mode was able to be selected there. llvm-svn: 256483
* [X86][AVX512] add vmovss/sd missing encoding Asaf Badouh2015-12-061-0/+55
| | | | | | Differential Revision: http://reviews.llvm.org/D14701 llvm-svn: 254875
* [X86][AVX512] add comi with SaeAsaf Badouh2015-12-021-0/+127
| | | | | | | | add builtin_ia32_vcomisd and builtin_ia32_vcomisd Differential Revision: http://reviews.llvm.org/D14331 llvm-svn: 254493
* AVX512:Implemented encoding for the vmovq.s instruction.Igor Breger2015-11-291-0/+16
| | | | | | Differential Revision: http://reviews.llvm.org/D14810 llvm-svn: 254248
* AVX512: Implemented encoding, intrinsics and DAG lowering for VMOVDDUP ↵Igor Breger2015-11-191-0/+36
| | | | | | | | instructions. Differential Revision: http://reviews.llvm.org/D14702 llvm-svn: 253548
* AVX512: Implemented encoding for the vmovss.s and vmovsd.s instructions.Igor Breger2015-11-191-0/+96
| | | | | | Differential Revision: http://reviews.llvm.org/D14771 llvm-svn: 253547
* AVX512: Implemented encoding for the follow instructions.Igor Breger2015-11-191-0/+384
| | | | | | | | vmovapd.s, vmovaps.s, vmovdqa32.s, vmovdqa64.s, vmovdqu16.s, vmovdqu32.s, vmovdqu64.s, vmovdqu8.s, vmovupd.s, vmovups.s Differential Revision: http://reviews.llvm.org/D14768 llvm-svn: 253546
* AVX512: Implemented encoding and intrinsics for VMOVSHDUP/VMOVSLDUP ↵Igor Breger2015-11-161-0/+72
| | | | | | | | instructions. Differential Revision: http://reviews.llvm.org/D14322 llvm-svn: 253185
* Revert r253160.Igor Breger2015-11-151-72/+0
| | | | | | It broke layering violation. Reproducible with BUILD_SHARED_LIBS=ON. llvm-svn: 253163
* AVX512: Implemented encoding and intrinsics for VMOVSHDUP/VMOVSLDUP ↵Igor Breger2015-11-151-0/+72
| | | | | | | | instructions. Differential Revision: http://reviews.llvm.org/D14322 llvm-svn: 253160
* AVX512 : Implemented encoding and DAG lowering for VMOVHPS/PD and VMOVLPS/PD ↵Igor Breger2015-11-101-0/+192
| | | | | | | | instructions. Differential Revision: http://reviews.llvm.org/D14492 llvm-svn: 252592
* revert rev. 252153 due to build failure on ubuntuAsaf Badouh2015-11-051-127/+0
| | | | | | [X86][AVX512] add comi with Sae llvm-svn: 252154
* [X86][AVX512] add comi with SaeAsaf Badouh2015-11-051-0/+127
| | | | | | | | add builtin_ia32_vcomisd and builtin_ia32_vcomisd Differential Revision: http://reviews.llvm.org/D14331 llvm-svn: 252153
* AVX512: add encoding tests for vmovq/d instructions.Igor Breger2015-11-031-1/+346
| | | | llvm-svn: 251903
* [X86][AVX512] [X86][AVX512] add convert float to halfAsaf Badouh2015-10-271-0/+56
| | | | | | | | convert float to half with mask/maskz for the reg to reg version and mask for the reg to mem version (there is no maskz version for reg to mem). Differential Revision: http://reviews.llvm.org/D14113 llvm-svn: 251409
* [X86][AVX512] extend vcvtph2ps to support xmm/ymm and sae versionsAsaf Badouh2015-10-221-0/+39
| | | | | | Differential Revision: http://reviews.llvm.org/D13945 llvm-svn: 251018
* AVX512: Implemented encoding and intrinsics for VPBROADCASTB/W/D/Q instructions.Igor Breger2015-10-201-0/+124
| | | | | | Differential Revision: http://reviews.llvm.org/D13884 llvm-svn: 250819
* AVX512: Implemented encoding and intrinsics for vpternlogd/q.Igor Breger2015-10-151-0/+121
| | | | | | Differential Revision: http://reviews.llvm.org/D13768 llvm-svn: 250396
* AVX512: Implemented encoding and intrinsics for VPERMILPS/PD instructions.Igor Breger2015-10-041-0/+232
| | | | | | | | Added tests for intrinsics and encoding. Differential Revision: http://reviews.llvm.org/D12690 llvm-svn: 249261
* [X86][AVX512] add masked version for RSQRT14 & RCP14 Scalar FPAsaf Badouh2015-09-211-0/+143
| | | | | | Differential Revision: http://reviews.llvm.org/D12524 llvm-svn: 248147
* AVX512: Implemented encoding and intrinsics for vcmpss/sd.Igor Breger2015-09-201-0/+88
| | | | | | | | Added tests for intrinsics and encoding. Differential Revision: http://reviews.llvm.org/D12593 llvm-svn: 248121
* [X86][AVX512] extend support in Scalar conversionAsaf Badouh2015-09-201-0/+1311
| | | | | | | | | | add scalar FP to Int conversion with truncation intrinsics add scalar conversion FP32 from/to FP64 intrinsics add rounding mode and SAE mode encoding for these intrinsics Differential Revision: http://reviews.llvm.org/D12665 llvm-svn: 248117
* AVX512: vsqrtss/sd encoding and intrinsics implementation.Igor Breger2015-09-201-0/+104
| | | | | | | | Added tests for intrinsics and encoding. Differential Revision: http://reviews.llvm.org/D12102 llvm-svn: 248116
* AVX512: Implement instructions encoding, lowering and intrinsicsIgor Breger2015-09-201-0/+160
| | | | | | | | | vinserti64x4, vinserti64x2, vinserti32x8, vinserti32x4, vinsertf64x4, vinsertf64x2, vinsertf32x8, vinsertf32x4 Added tests for encoding, lowering and intrinsics. Differential Revision: http://reviews.llvm.org/D11893 llvm-svn: 248111
* AVX512: Implemented encoding and intrinsics forIgor Breger2015-09-101-0/+192
| | | | | | | | | vextracti64x4 ,vextracti64x2, vextracti32x8, vextracti32x4, vextractf64x4, vextractf64x2, vextractf32x8, vextractf32x4 Added tests for intrinsics and encoding. Differential Revision: http://reviews.llvm.org/D11802 llvm-svn: 247276
* Revert "AVX512: Implemented encoding and intrinsics for vextracti64x4 ↵Renato Golin2015-09-091-192/+0
| | | | | | | | ,vextracti64x2, vextracti32x8, vextracti32x4, vextractf64x4, vextractf64x2, vextractf32x8, vextractf32x4 Added tests for intrinsics and encoding." This reverts commit r247149, as it was breaking numerous buildbots of varied architectures. llvm-svn: 247177
* AVX512: Implemented encoding and intrinsics forIgor Breger2015-09-091-0/+192
| | | | | | | | | vextracti64x4 ,vextracti64x2, vextracti32x8, vextracti32x4, vextractf64x4, vextractf64x2, vextractf32x8, vextractf32x4 Added tests for intrinsics and encoding. Differential Revision: http://reviews.llvm.org/D11802 llvm-svn: 247149
* AVX512: kunpck encoding implementation Igor Breger2015-09-081-0/+4
| | | | | | | | Added tests for encoding. Differential Revision: http://reviews.llvm.org/D12061 llvm-svn: 247010
* AVX512: Implemented encoding and intrinsics for VGETMANTPD/S , VGETMANTSD/S ↵Igor Breger2015-09-021-0/+232
| | | | | | | | | | instructions Added tests for intrinsics and encoding. Differential Revision: http://reviews.llvm.org/D11593 llvm-svn: 246642
* AVX512: Implemented encoding and intrinsics for vshufps/d.Igor Breger2015-09-021-0/+120
| | | | | | | | Added tests for intrinsics and encoding. Differential Revision: http://reviews.llvm.org/D11709 llvm-svn: 246640
* AVX512: ktest implemantationIgor Breger2015-08-311-0/+4
| | | | | | | | Added tests for encoding. Differential Revision: http://reviews.llvm.org/D11979 llvm-svn: 246439
* AVX512: Add encoding tests for vscatter instructionsIgor Breger2015-08-311-0/+64
| | | | | | Differential Revision: http://reviews.llvm.org/D11941 llvm-svn: 246431
* AVX512: Implemented encoding and intrinsics for VGETEXPSS/D instructionsIgor Breger2015-07-281-0/+80
| | | | | | | | Added tests for intrinsics and encoding. Differential Revision: http://reviews.llvm.org/D11528 llvm-svn: 243390
* Implemented encoding and intrinsics of the following instructionsIgor Breger2015-07-261-0/+448
| | | | | | | | | | vunpckhps/pd, vunpcklps/pd, vpunpcklbw, vpunpckhbw, vpunpcklwd, vpunpckhwd, vpunpckldq, vpunpckhdq, vpunpcklqdq, vpunpckhqdq Added tests for intrinsics and encoding. Differential Revision: http://reviews.llvm.org/D11509 llvm-svn: 243246
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