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* [SystemZ] Add all remaining instructionsUlrich Weigand2017-06-301-0/+1411
| | | | | | | | | | | This adds all remaining instructions that were still missing, mostly privileged and semi-privileged system-level instructions. These are provided for use with the assembler and disassembler only. This brings the LLVM assembler / disassembler to parity with the GNU binutils tools. llvm-svn: 306876
* [SystemZ] Add decimal floating-point instructionsUlrich Weigand2017-05-301-0/+699
| | | | | | | | | This adds assembler / disassembler support for the decimal floating-point instructions. Since LLVM does not yet have support for decimal float types, these cannot be used for codegen at this point. llvm-svn: 304203
* [SystemZ] Add hexadecimal floating-point instructionsUlrich Weigand2017-05-301-0/+1386
| | | | | | | | This adds assembler / disassembler support for the hexadecimal floating-point instructions. Since the Linux ABI does not use any hex float data types, these are not useful for codegen. llvm-svn: 304202
* [SystemZ] Add missing assembler/disassembler testsUlrich Weigand2017-05-301-0/+50
| | | | | | | A few instructions that are actually correctly supported in the assembler and disassembler did not have any tests. llvm-svn: 304200
* [SystemZ] Add miscellaneous instructionsUlrich Weigand2017-05-101-0/+92
| | | | | | | | This adds a few missing instructions for the assembler and disassembler. Those should be the last missing general- purpose (Chapter 7) instructions for the z10 ISA. llvm-svn: 302667
* [SystemZ] Add missing arithmetic instructionsUlrich Weigand2017-05-101-0/+490
| | | | | | | | | This adds the remaining general arithmetic instructions for assembler / disassembler use. Most of these are not useful for codegen; a few might be, and those are listed in the README.txt for future improvements. llvm-svn: 302665
* [SystemZ] Add decimal integer instructionsUlrich Weigand2017-05-101-0/+642
| | | | | | | This adds the set of decimal integer (BCD) instructions for assembler / disassembler use. llvm-svn: 302646
* [SystemZ] Add crypto instructionsUlrich Weigand2017-05-101-0/+50
| | | | | | | This adds the set of message-security assist instructions for assembler / disassembler use. llvm-svn: 302645
* [SystemZ] Add translate/convert instructionsUlrich Weigand2017-05-101-0/+276
| | | | | | | This adds the set of character-set translate and convert instructions for assembler / disassembler use. llvm-svn: 302644
* [SystemZ] Add missing memory/string instructionsUlrich Weigand2017-05-101-0/+142
| | | | | | | This adds a number of missing memory and string instructions for assembler / disassembler use. llvm-svn: 302643
* [SystemZ] Reformat assembler/disassembler testsUlrich Weigand2017-05-101-221/+220
| | | | | | | | The assembler and disassmebler test cases started out formatted and sorted in a particular way, but this got lost over time as patches were added. Reformat them again. NFC. llvm-svn: 302642
* [SystemZ] Support remaining atomic instructionsUlrich Weigand2016-12-021-0/+152
| | | | | | | | Add assembler support for all atomic instructions that weren't already supported. Some of those could be used to implement codegen for 128-bit atomic operations, but this isn't done here yet. llvm-svn: 288526
* [SystemZ] Support floating-point control register instructionsUlrich Weigand2016-12-021-0/+94
| | | | | | | | | | Add assembler support for instructions manipulating the FPC. Also add codegen support via the GCC compatibility builtins: __builtin_s390_sfpc __builtin_s390_efpc llvm-svn: 288525
* [SystemZ] Add remaining branch instructionsUlrich Weigand2016-11-281-0/+244
| | | | | | | | | | | | | | | | | This patch adds assembler support for the remaining branch instructions: the non-relative branch on count variants, and all variants of branch on index. The only one of those that can be readily exploited for code generation is BRCTH (branch on count using a high 32-bit register as count). Do use it, however, it is necessary to also introduce a hew CHIMux pseudo to allow comparisons of a 32-bit value agains a short immediate to go into a high register as well (implemented via CHI/CIH). This causes a bit of codegen changes overall, but those have proven to be neutral (or even beneficial) in performance measurements. llvm-svn: 288029
* [SystemZ] Use LLGT(R) instructionsUlrich Weigand2016-11-111-0/+30
| | | | | | | | | | | | | This adds support for the 31-to-64-bit zero extension instructions LLGT and LLGTR and uses them for code generation where appropriate. Since this operation can also be performed via RISBG, we have to update SystemZDAGToDAGISel::tryRISBGZero so that we prefer LLGT over RISBG in case both are possible. The patch includes some simplification to the tryRISBGZero code; this is not intended to cause any (further) functional change in codegen. llvm-svn: 286585
* [SystemZ] Add program mask and addressing mode instructionsUlrich Weigand2016-11-081-0/+64
| | | | | | | | | Add several instructions that operate on the program mask or the addressing mode. These are not really needed for code generation under Linux, but are provided for completeness for the assembler/disassembler. llvm-svn: 286284
* [SystemZ] Model access registers as LLVM registersUlrich Weigand2016-11-081-0/+161
| | | | | | | | | | | | | Add the 16 access registers as LLVM registers. This allows removing a lot of special cases in the assembler and disassembler where we were handling access registers; this can all just use the generic register code now. Also add a bunch of instructions to operate on access registers, for assembler/disassembler use only. No change in code generation intended. llvm-svn: 286283
* [SystemZ] Refactor branch and conditional instruction patternsUlrich Weigand2016-11-081-0/+128
| | | | | | | | | | | | | | | | | Rework patterns for branches, call & return instructions, compare-and-branch, compare-and-trap, and conditional move instructions. In particular, simplify creation of patterns for the extended opcodes of instructions that take a CC mask. Also, use semantical instruction classes for all the instructions instead of open-coding them in SystemZInstrInfo.td. Adds a couple of the basic branch instructions (that are unused for codegen) for the assembler/disassembler. llvm-svn: 286263
* [SystemZ] Fix encoding of MVCK and .insn ssUlrich Weigand2016-10-311-6/+8
| | | | | | | | | | | | | | | | | | | | LLVM currently treats the first operand of MVCK as if it were a regular base+index+displacement address. However, it is in fact a base+displacement combined with a length register field. While the two might look syntactically similar, there are two semantic differences: - %r0 is a valid length register, even though it cannot be used as an index register. - In an expression with just a single register like 0(%rX), the register is treated as base with normal addresses, while it is treated as the length register (with an empty base) for MVCK. Fixed by adding a new operand parser class BDRAddr and reworking the assembler parser to distinguish between address + length register operands and regular addresses. llvm-svn: 285574
* [SystemZ] Add missing classes and instructionsZhan Jun Liau2016-08-051-0/+151
| | | | | | | | | | | | | | | | Summary: Add instruction formats E, RSI, SSd, SSE, and SSF. Added BRXH, BRXLE, PR, MVCK, STRAG, and ECTG instructions to test out those formats. Reviewers: uweigand Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D23179 llvm-svn: 277822
* [SystemZ] Add support for missing instructionsZhan Jun Liau2016-07-081-0/+307
| | | | | | | | | | | | | | | | | Summary: Add support to allow clang integrated assembler to recognize some missing instructions, for openssl. Instructions are: LM, LMH, LMY, STM, STMH, STMY, ICM, ICMH, ICMY, SLA, SLAK, TML, TMH, EX, EXRL. Reviewers: uweigand Subscribers: koriakin, llvm-commits Differential Revision: http://reviews.llvm.org/D22050 llvm-svn: 274869
* [SystemZ] Add floating-point test data class instructions.Marcin Koscielnicki2016-06-291-0/+48
| | | | | | | These are not used by CodeGen yet - ISD combiners creating the new node will come in subsequent patches. llvm-svn: 274108
* [SystemZ] Support Compare and TrapsZhan Jun Liau2016-06-101-0/+172
| | | | | | | | | | | | Support and generate Compare and Traps like CRT, CIT, etc. Support Trap as legal DAG opcodes and generate "j .+2" for them by default. Add support for Conditional Traps and use the If Converter to convert them into the corresponding compare and trap opcodes. Differential Revision: http://reviews.llvm.org/D21155 llvm-svn: 272419
* [SystemZ] Support LRVH and STRVH opcodesBryan Chan2016-05-161-0/+44
| | | | | | | | | | | | Summary: On Linux, /usr/include/bits/byteswap-16.h defines __byteswap_16(x) as an inlined LRVH (Load Reversed Half-word) instruction. The SystemZ back-end did not support this opcode and the inlined assembly would cause a fatal error. Reviewers: bryanpkc, uweigand Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D18732 llvm-svn: 269688
* [SystemZ] Add support for additional branch extended mnemonicsKit Barton2016-05-101-0/+36
| | | | | | | | | | | | | Added support for extended mnemonics for the following branch instructions and load/store-on-condition opcodes: BR, LOCR, LOCGR, LOC, LOCG, STOC, STOCG Phabricator: http://reviews.llvm.org/D19729 Committing on behalf of Zhan Liau llvm-svn: 269106
* [SystemZ] Add SVC instructionUlrich Weigand2016-04-111-0/+10
| | | | | | | | | This is going to be useful for inline assembly only. Author: koriakin Differential Revision: http://reviews.llvm.org/D18952 llvm-svn: 265943
* [SystemZ] Add compare-and-branch instructions to MCUlrich Weigand2016-04-041-0/+624
| | | | | | | | | | | | This adds MC support for fused compare + indirect branch instructions, ie. CRB, CGRB, CLRB, CLGRB, CIB, CGIB, CLIB, CLGIB. They aren't actually generated yet -- this is preparation for their use for conditional returns in the next iteration of D17339. Author: koriakin Differential Revision: http://reviews.llvm.org/D18742 llvm-svn: 265296
* [SystemZ] Add nop and nopr InstAliases.Jonas Paulsson2016-03-301-0/+6
| | | | | | | | | | For compatability with GAS, nop and nopr are recognized as alises for bc and bcr, respectively. A mask of 0 turns these instructions effectively into no-operations. Reviewed by Ulrich Weigand. llvm-svn: 264875
* [SystemZ] Add assembly instructions for obtaining clock values as well as ↵Ulrich Weigand2015-10-011-0/+56
| | | | | | | | | | | CPU features Provide assembler support for STCK, STCKF, STCKE, and STFLE. Author: joncmu Differential Revision: http://reviews.llvm.org/D13299 llvm-svn: 249015
* [SystemZ] Add the general form of BCRRichard Sandiford2013-11-131-0/+91
| | | | | | At the moment this is just the MC support. llvm-svn: 194585
* [SystemZ] Add unsigned compare-and-branch instructionsRichard Sandiford2013-09-181-0/+914
| | | | | | | | | | | | | | | For some reason I never got around to adding these at the same time as the signed versions. No idea why. I'm not sure whether this SystemZII::BranchC* stuff is useful, or whether it should just be replaced with an "is normal" flag. I'll leave that for later though. There are some boundary conditions that can be tweaked, such as preferring unsigned comparisons for equality with [128, 256), and "<= 255" over "< 256", but again I'll leave those for a separate patch. llvm-svn: 190930
* [SystemZ] Add TM and TMYRichard Sandiford2013-09-101-0/+38
| | | | | | | | | | | | | | | | | | | | | | | The main complication here is that TM and TMY (the memory forms) set CC differently from the register forms. When the tested bits contain some 0s and some 1s, the register forms set CC to 1 or 2 based on the value the uppermost bit. The memory forms instead set CC to 1 regardless of the uppermost bit. Until now, I've tried to make it so that a branch never tests for an impossible CC value. E.g. NR only sets CC to 0 or 1, so branches on the result will only test for 0 or 1. Originally I'd tried to do the same thing for TM and TMY by using custom matching code in ISelDAGToDAG. That ended up being very ugly though, and would have meant duplicating some of the chain checks that the common isel code does. I've therefore gone for the simpler alternative of adding an extra operand to the TM DAG opcode to say whether a memory form would be OK. This means that the inverse of a "TM;JE" is "TM;JNE" rather than the more precise "TM;JNLE", just like the inverse of "TMLL;JE" is "TMLL;JNE". I suppose that's arguably less confusing though... llvm-svn: 190400
* [SystemZ] Add NC, OC and XCRichard Sandiford2013-09-051-0/+78
| | | | | | | For now these are just used to handle scalar ANDs, ORs and XORs in which all operands are memory. llvm-svn: 190041
* [SystemZ] Add support for TMHH, TMHL, TMLH and TMLLRichard Sandiford2013-08-281-0/+40
| | | | | | | | | For now just handles simple comparisons of an ANDed value with zero. The CC value provides enough information to do any comparison for a 2-bit mask, and some nonzero comparisons with more populated masks, but that's all future work. llvm-svn: 189469
* [SystemZ] Add basic prefetch supportRichard Sandiford2013-08-231-0/+59
| | | | | | Just the instructions and intrinsics for now. llvm-svn: 189100
* [SystemZ] Add negative integer absolute (load negative)Richard Sandiford2013-08-191-0/+30
| | | | | | | | For now this matches the equivalent of (neg (abs ...)), which did hit a few times in projects/test-suite. We should probably also match cases where absolute-like selects are used with reversed arguments. llvm-svn: 188671
* [SystemZ] Add integer absolute (load positive)Richard Sandiford2013-08-191-0/+30
| | | | llvm-svn: 188670
* [SystemZ] Use SRST to implement strlen and strnlenRichard Sandiford2013-08-161-0/+10
| | | | | | It would also make sense to use it for memchr; I'm working on that now. llvm-svn: 188547
* [SystemZ] Use MVST to implement strcpy and stpcpyRichard Sandiford2013-08-161-0/+10
| | | | llvm-svn: 188546
* [SystemZ] Use CLST to implement strcmpRichard Sandiford2013-08-161-0/+10
| | | | llvm-svn: 188544
* [SystemZ] Add a definition of the CLC instructionRichard Sandiford2013-08-121-0/+26
| | | | llvm-svn: 188162
* [SystemZ] Add a definition of the IPM instructionRichard Sandiford2013-08-121-0/+8
| | | | llvm-svn: 188161
* [SystemZ] Add floating-point load-and-test instructionsRichard Sandiford2013-08-071-0/+30
| | | | | | These instructions can also be used as comparisons with zero. llvm-svn: 187882
* [SystemZ] Add definitions for BRCT and BRCTGRichard Sandiford2013-08-051-0/+32
| | | | llvm-svn: 187721
* [SystemZ] Add LOAD AND TEST instructionsRichard Sandiford2013-08-051-0/+96
| | | | | | Just the definitions and MC support. The next patch uses them for codegen. llvm-svn: 187719
* [SystemZ] Start adding z196 and zEC12 supportRichard Sandiford2013-07-191-0/+1
| | | | | | | | | | | | This first step just adds definitions for SLLK, SRLK and SRAK. The next patch will actually make use of them during codegen. insn-bad.s tests that some form of error is reported when using these instructions on z10. More work is needed to get the "instruction requires: distinct-ops" that we'd ideally like, so I've stubbed that part out for now. I'll come back and make it mandatory once the necessary changes are in. llvm-svn: 186680
* [SystemZ] Add MC support for R[NOX]SBGRichard Sandiford2013-07-161-0/+48
| | | | | | CodeGen support will come later. llvm-svn: 186401
* [SystemZ] Allow 8-bit operands to RISBGRichard Sandiford2013-07-111-4/+4
| | | | | | | | | | | | RISBG has three 8-bit operands (I3, I4 and I5). I'd originally restricted all three to 6 bits, since that's the only range we intended to use at the time. However, the top bit of I4 acts as a "zero" flag for RISBG, while the top bit of I3 acts as a "test" flag for RNSBG & co. This patch therefore allows them to have the full 8-bit range. I've left the fifth operand as a 6-bit value for now since the upper 2 bits have no defined meaning. llvm-svn: 186070
* [SystemZ] Add the MVC instructionRichard Sandiford2013-07-021-0/+26
| | | | | | | | | This is the first use of D(L,B) addressing, which required a fair bit of surgery. For that reason, the patch just adds the instruction definition and the associated assembler and disassembler support. A later patch will actually make use of it for codegen. llvm-svn: 185433
* [SystemZ] Immediate compare-and-branch supportRichard Sandiford2013-05-291-0/+466
| | | | | | This patch adds support for the CIJ and CGIJ instructions. llvm-svn: 182846
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