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* [Sparc] Remove execute permissions from non-executable text filesDaniel Cederman2017-05-171-0/+0
| | | | | | | | | | | | Reviewers: jyknight, lero_chris, venkatra Reviewed By: jyknight Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D27127 llvm-svn: 303245
* Don't pass a Reloc::Model to MC.Rafael Espindola2016-05-181-2/+2
| | | | | | | | | | | | MC only needs to know if the output is PIC or not. It never has to decide about creating GOTs and PLTs for example. The only thing that MC itself uses this information for is expanding "macros" in sparc and mips. The rest I am pretty sure could be moved to CodeGen. This is a cleanup and isolates the code from future changes to Reloc::Model. llvm-svn: 269909
* [Sparc][LEON] Add LEON-specific CASA instruction.Chris Dewhurst2016-05-161-2/+10
| | | | | | Differental Revision: http://reviews.llvm.org/D20098 llvm-svn: 269644
* [Sparc][LEON] Add UMAC and SMAC instruction support for Sparc LEON subtargetsChris Dewhurst2016-05-091-0/+12
| | | | | | | | | | | | This change adds SMAC (signed multiply-accumulate) and UMAC (unsigned multiply-accumulate) for LEON subtargets of the Sparc processor. The new files LeonFeatures.td and leon-instructions.ll will both be expanded in future, so I want to leave them separate as small files for this review, to be expanded in future check-ins. Note: The functions are provided only for inline-assembly provision. No DAG selection is provided. Differential Revision: http://reviews.llvm.org/D19911 llvm-svn: 268908
* Sparc: silently ignore .proc assembler directiveDouglas Katzman2016-03-281-0/+4
| | | | | | Differential Revision: http://reviews.llvm.org/D18463 llvm-svn: 264579
* This change adds co-processor condition branching and conditional traps to ↵Chris Dewhurst2016-03-094-6/+638
| | | | | | | | | | | | | | | | the Sparc back-end. This will allow inline assembler code to utilize these features, but no automatic lowering is provided, except for the previously provided @llvm.trap, which lowers to "ta 5". The change also separates out the different assembly language syntaxes for V8 and V9 Sparc. Previously, only V9 Sparc assembly syntax was provided. The change also corrects the selection order of trap disassembly, allowing, e.g. "ta %g0 + 15" to be rendered, more readably, as "ta 15", ignoring the %g0 register. This is per the sparc v8 and v9 manuals. Check-in includes many extra unit tests to check this works correctly on both V8 and V9 Sparc processors. Code Reviewed at http://reviews.llvm.org/D17960. llvm-svn: 263044
* Addition of tests to previous check-in. Tests for coprocessor register usage ↵Chris Dewhurst2016-02-271-0/+72
| | | | | | | | | | | | | | | | in Sparc. Previous check-in message was: The patch adds missing registers and instructions to complete all the registers supported by the Sparc v8 manual. These are all co-processor registers, with the exception of the floating-point deferred-trap queue register. Although these will not be lowered automatically by any instructions, it allows the use of co-processor instructions implemented by inline-assembly. Code Reviewed at http://reviews.llvm.org/D17133, with the exception of a very small change in brace placement in SparcInstrInfo.td, which was formerly causing a problem in the disassembly of the %fq register. llvm-svn: 262135
* The patch adds missing registers and instructions to complete all the ↵Chris Dewhurst2016-02-272-11/+22
| | | | | | | | | | | | | registers supported by the Sparc v8 manual. These are all co-processor registers, with the exception of the floating-point deferred-trap queue register. Although these will not be lowered automatically by any instructions, it allows the use of co-processor instructions implemented by inline-assembly. Code Reviewed at http://reviews.llvm.org/D17133, with the exception of a very small change in brace placement in SparcInstrInfo.td, which was formerly causing a problem in the disassembly of the %fq register. llvm-svn: 262133
* Reverting breaking change. Sorry.Chris Dewhurst2016-02-261-19/+11
| | | | llvm-svn: 262007
* Reviewed at reviews.llvm.org/D17133Chris Dewhurst2016-02-261-11/+19
| | | | llvm-svn: 262005
* [SPARC] Repair floating-point condition encodings in assembly parser.James Y Knight2016-02-102-0/+25
| | | | | | | | | | | | | | | The encodings for floating point conditions A(lways) and N(ever) were incorrectly specified for the assembly parser, per Sparc manual v8 page 121. This change corrects that mistake. Also, strangely, all of the branch instructions already had MC test cases, except for the broken ones. Added the tests. Patch by Chris Dewhurst Differential Revision: http://reviews.llvm.org/D17074 llvm-svn: 260390
* Update test to take into account for r251271.David Majnemer2015-10-261-1/+1
| | | | llvm-svn: 251272
* [SPARCv9] Add support for the rdpr/wrpr instructions.Joerg Sonnenberger2015-10-041-0/+183
| | | | llvm-svn: 249262
* Fix relocation used for GOT references in non-PIC mode. Fix relocationsJoerg Sonnenberger2015-10-011-11/+33
| | | | | | | | for "set" pseudo op in PIC mode. Differential Revision: http://reviews.llvm.org/D13173 llvm-svn: 249086
* [SPARC] Add mulscc.Joerg Sonnenberger2015-09-171-0/+6
| | | | llvm-svn: 247940
* [SPARC] Both GNU and Solaris as support eq as condition code for integer ops.Joerg Sonnenberger2015-09-161-0/+4
| | | | llvm-svn: 247804
* [SPARC] Recognize st/stx operations with %fsr argument too.Joerg Sonnenberger2015-09-162-0/+16
| | | | llvm-svn: 247794
* Fix CHECK directives that weren't checking.Hans Wennborg2015-08-311-5/+5
| | | | llvm-svn: 246485
* [Sparc]: correct the 'set' synthetic instructionDouglas Katzman2015-08-202-2/+78
| | | | | | Differential Revision: http://reviews.llvm.org/D12194 llvm-svn: 245575
* [Sparc]: asm-only support for the ldstub instruction.Douglas Katzman2015-08-191-0/+9
| | | | llvm-svn: 245485
* [SPARC] Enable writing to floating-point-state register.Douglas Katzman2015-08-192-0/+16
| | | | llvm-svn: 245475
* Map %fprs to %asr6 in the Sparc assembler parser.Joerg Sonnenberger2015-08-191-0/+6
| | | | llvm-svn: 245437
* Load/store instructions for floating points with address space require SparcV9.Joerg Sonnenberger2015-08-182-22/+40
| | | | | | | | To properly handle this, define the *a instructions as separate instruction classes by refactoring the LoadA and StoreA multiclasses. Move the instruction tests into the sparcv9 file to test the difference. llvm-svn: 245360
* [SPARC]: recognize '.' as the start of an assembler expression.Douglas Katzman2015-08-171-0/+7
| | | | llvm-svn: 245232
* Add lduw and lwua aliases for SPARCv9.Joerg Sonnenberger2015-08-101-0/+17
| | | | llvm-svn: 244535
* Load/store for float registers from/to alternate space.Joerg Sonnenberger2015-08-101-0/+29
| | | | llvm-svn: 244532
* Add support for the signx instrution alias of SPARCv9.Joerg Sonnenberger2015-08-101-0/+9
| | | | llvm-svn: 244519
* [Sparc] Implement i64 load/store support for 32-bit sparc.James Y Knight2015-08-101-0/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The LDD/STD instructions can load/store a 64bit quantity from/to memory to/from a consecutive even/odd pair of (32-bit) registers. They are part of SparcV8, and also present in SparcV9. (Although deprecated there, as you can store 64bits in one register). As recommended on llvmdev in the thread "How to enable use of 64bit load/store for 32bit architecture" from Apr 2015, I've modeled the 64-bit load/store operations as working on a v2i32 type, rather than making i64 a legal type, but with few legal operations. The latter does not (currently) work, as there is much code in llvm which assumes that if i64 is legal, operations like "add" will actually work on it. The same assumption does not hold for v2i32 -- for vector types, it is workable to support only load/store, and expand everything else. This patch: - Adds a new register class, IntPair, for even/odd pairs of registers. - Modifies the list of reserved registers, the stack spilling code, and register copying code to support the IntPair register class. - Adds support in AsmParser. (note that in asm text, you write the name of the first register of the pair only. So the parser has to morph the single register into the equivalent paired register). - Adds the new instructions themselves (LDD/STD/LDDA/STDA). - Hooks up the instructions and registers as a vector type v2i32. Adds custom legalizer to transform i64 load/stores into v2i32 load/stores and bitcasts, so that the new instructions can actually be generated, and marks all operations other than load/store on v2i32 as needing to be expanded. - Copies the unfortunate SelectInlineAsm hack from ARMISelDAGToDAG. This hack undoes the transformation of i64 operands into two arbitrarily-allocated separate i32 registers in SelectionDAGBuilder. and instead passes them in a single IntPair. (Arbitrarily allocated registers are not useful, asm code expects to be receiving a pair, which can be passed to ldd/std.) Also adds a bunch of test cases covering all the bugs I've added along the way. Differential Revision: http://reviews.llvm.org/D8713 llvm-svn: 244484
* [SPARC] Don't compare arch name as a string, use the enum instead.Douglas Katzman2015-08-061-1/+4
| | | | | | Fixes PR22695 llvm-svn: 244221
* [Sparc] Fix disassembly of popc instruction.James Y Knight2015-08-051-0/+5
| | | | | | | | And add tests. Patch by David Wiberg! llvm-svn: 244064
* [Sparc] Add more instruction aliases.James Y Knight2015-07-062-3/+131
| | | | | | | | | These are mostly from the chart in the SparcV8 spec, section "A.3 Synthetic Instructions". Differential Revision: http://reviews.llvm.org/D9834 llvm-svn: 241461
* [Sparc] Add support for flush instruction.James Y Knight2015-07-061-0/+10
| | | | | | Differential Revision: http://reviews.llvm.org/D9833 llvm-svn: 241460
* Revert r240302 ("Bring r240130 back.").Daniel Jasper2015-06-231-2/+2
| | | | | | | | | | | | | This causes errors like: ld: error: blah.o: requires dynamic R_X86_64_PC32 reloc against '' which may overflow at runtime; recompile with -fPIC blah.cc:function f(): error: undefined reference to '' blah.o:g(): error: undefined reference to '' I have not yet come up with an appropriate reproduction. llvm-svn: 240394
* Bring r240130 back.Rafael Espindola2015-06-221-2/+2
| | | | | | | | | | | | | | | | | | | | | | Now that pr23900 is fixed, we can bring it back with no changes. Original message: Make all temporary symbols unnamed. What this does is make all symbols that would otherwise start with a .L (or L on MachO) unnamed. Some of these symbols still show up in the symbol table, but we can just make them unnamed. In order to make sure we produce identical results when going thought assembly, all .L (not just the compiler produced ones), are now unnamed. Running llc on llvm-as.opt.bc, the peak memory usage goes from 208.24MB to 205.57MB. llvm-svn: 240302
* Revert 240130, it caused crashes (repro in PR23900).Nico Weber2015-06-191-2/+2
| | | | llvm-svn: 240193
* Make all temporary symbols unnamed.Rafael Espindola2015-06-191-2/+2
| | | | | | | | | | | | | | | | What this does is make all symbols that would otherwise start with a .L (or L on MachO) unnamed. Some of these symbols still show up in the symbol table, but we can just make them unnamed. In order to make sure we produce identical results when going thought assembly, all .L (not just the compiler produced ones), are now unnamed. Running llc on llvm-as.opt.bc, the peak memory usage goes from 208.24MB to 205.57MB. llvm-svn: 240130
* [SPARC] Repair GOT references to internal symbols.James Y Knight2015-06-181-3/+12
| | | | | | | | | | They had been getting emitted as a section + offset reference, which is bogus since the value needs to be the offset within the GOT, not the actual address of the symbol's object. Differential Revision: http://reviews.llvm.org/D10441 llvm-svn: 240020
* [llvm-mc] The object form of the GNU triple should be the same as the string ↵Daniel Sanders2015-06-161-2/+2
| | | | | | | | | | | | | | | | | | | | | | | form. Summary: GetTarget() may modify TripleName without also updating TheTriple. This can lead to situations where the MCObjectStreamer has a different triple to the rest of LLVM. This inconsistency caused sparc-little-endian.s to pass on Windows because most of LLVM had sparcel-pc-win32 while MCObjectStreamer had "". I believe the same kind of thing was also true of Darwin. Reviewers: rengolin Reviewed By: rengolin Subscribers: llvm-commits, rengolin, rafael Differential Revision: http://reviews.llvm.org/D10450 llvm-svn: 239808
* Sparc: support the "set" synthetic instruction.James Y Knight2015-05-181-0/+17
| | | | | | | | | This pseudo-instruction expands into 'sethi' and 'or' instructions, or, just one of them, if the other isn't necessary for a given value. Differential Revision: http://reviews.llvm.org/D9089 llvm-svn: 237585
* Sparc: Support PSR, TBR, WIM read/write instructions.James Y Knight2015-05-181-0/+18
| | | | | | Differential Revision: http://reviews.llvm.org/D8971 llvm-svn: 237582
* Sparc: Add the "alternate address space" load/store instructions.James Y Knight2015-05-183-8/+29
| | | | | | | | | | | | | | | | | | - Adds support for the asm syntax, which has an immediate integer "ASI" (address space identifier) appearing after an address, before a comma. - Adds the various-width load, store, and swap in alternate address space instructions. (ldsba, ldsha, lduba, lduha, lda, stba, stha, sta, swapa) This does not attempt to hook these instructions up to pointer address spaces in LLVM, although that would probably be a reasonable thing to do in the future. Differential Revision: http://reviews.llvm.org/D8904 llvm-svn: 237581
* Add support for the Sparc implementation-defined "ASR" registers.James Y Knight2015-05-181-0/+17
| | | | | | | | | | (Note that register "Y" is essentially just ASR0). Also added some test cases for divide and multiply, which had none before. Differential Revision: http://reviews.llvm.org/D8670 llvm-svn: 237580
* [Sparc] Repair fixups in little endian mode.James Y Knight2015-05-011-0/+18
| | | | | | Differential Revision: http://reviews.llvm.org/D9434 llvm-svn: 236324
* Make Sparc assembler accept parenthesized constant expressions.Douglas Katzman2015-04-291-0/+6
| | | | | | Differential Revision: http://reviews.llvm.org/D9087 llvm-svn: 236137
* Sparc: Prefer reg+reg address encoding when only one register used.James Y Knight2015-04-292-11/+11
| | | | | | | | | | | Reg+%g0 is preferred to Reg+imm0 by the manual, and is what GCC produces. Futhermore, reg+imm is invalid for the (not yet supported) "alternate address space" instructions. Differential Revision: http://reviews.llvm.org/D8753 llvm-svn: 236107
* Sparc: Add alternate aliases for conditional branch instructions.James Y Knight2015-04-281-0/+24
| | | | llvm-svn: 236042
* Reduce verbiage of lit.local.cfg filesAlp Toker2014-06-091-2/+1
| | | | | | We can just split targets_to_build in one place and make it immutable. llvm-svn: 210496
* TableGen: fix operand counting for aliasesTim Northover2014-05-162-8/+8
| | | | | | | | | | | | | | | | | | | | | TableGen has a fairly dubious heuristic to decide whether an alias should be printed: does the alias have lest operands than the real instruction. This is bad enough (particularly with no way to override it), but it should at least be calculated consistently for both strings. This patch implements that logic: first get the *correct* string for the variant, in the same way as the Matcher, without guessing; then count the number of whitespace chars. There are basically 4 changes this brings about after the previous commits; all of these appear to be good, so I have changed the tests: + ARM64: we print "neg X, Y" instead of "sub X, xzr, Y". + ARM64: we skip implicit "uxtx" and "uxtw" modifiers. + Sparc: we print "mov A, B" instead of "or %g0, A, B". + Sparc: we print "fcmpX A, B" instead of "fcmpX %fcc0, A, B" llvm-svn: 208969
* [Sparc] Add trap on integer condition codes (Ticc) instructions to Sparc ↵Venkatraman Govindaraju2014-03-021-0/+7
| | | | | | backend. llvm-svn: 202670
* [Sparc] Add return/rett instruction to Sparc backend.Venkatraman Govindaraju2014-03-022-0/+5
| | | | llvm-svn: 202666
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