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* [RISCV] Add obsolete aliases of fscsr, frcsr (fssr, frsr)Edward Jones2019-10-031-0/+12
| | | | | | | | These old aliases were renamed, but are still used by some projects (eg newlib). Differential Revision: https://reviews.llvm.org/D68392 llvm-svn: 373618
* [RISCV] Support llvm-objdump -M no-aliases and -M numericSam Elliott2019-09-101-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | Summary: Now that llvm-objdump allows target-specific options, we match the `no-aliases` and `numeric` options for RISC-V, as supported by GNU objdump. This is done by overriding the variables used for the command-line options, so that the command-line options are still supported. This patch updates all tests using `llvm-objdump -riscv-no-aliases` to use `llvm-objdump -M no-aliases`. Reviewers: luismarques, asb Reviewed By: luismarques, asb Subscribers: pzheng, hiraditya, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, kito-cheng, shiva0217, jrtc27, MaskRay, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, Jim, s.egerton, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D66139 llvm-svn: 371534
* [RISCV] Add implied zero offset load/store alias patternsAlex Bradbury2019-02-211-0/+7
| | | | | | | | | | Allow load/store instructions with implied zero offset for compatibility with GNU assembler. Differential Revision: https://reviews.llvm.org/D57141 Patch by James Clarke. llvm-svn: 354581
* [RISCV] Support named operands for CSR instructions.Ana Pazos2018-10-041-13/+13
| | | | | | | | | | | | Reviewers: asb, mgrang Reviewed By: asb Subscribers: jocewei, mgorny, jfb, PkmX, MartinMosbeck, brucehoult, the_o, rkruppe, rogfer01, rbar, johnrusso, simoncook, jordy.potman.lists, sabuasal, niosHD, kito-cheng, shiva0217, zzheng, edward-jones Differential Revision: https://reviews.llvm.org/D46759 llvm-svn: 343822
* [RISCV] Accept fmv.s.x and fmv.x.s as mnemonic aliases for fmv.w.x and fmv.x.wAlex Bradbury2018-06-201-0/+7
| | | | | | | These instructions were renamed in version 2.2 of the user-level ISA spec, but the old name should also be accepted by standard tools. llvm-svn: 335154
* [RISCV] Add InstAlias definitions for fgt.{s|d}, fge.{s|d}Alex Bradbury2018-06-201-0/+7
| | | | | | | These are produced by GCC and supported by GAS, but not currently contained in the pseudoinstruction listing in the RISC-V ISA manual. llvm-svn: 335127
* [RISCV] Enable emission of alias instructions by defaultAlex Bradbury2017-12-151-4/+52
| | | | | | | | | | | | | | | | | | This patch switches the default for -riscv-no-aliases to false and updates all affected MC and CodeGen tests. As recommended in D41071, MC tests use the canonical instructions and the CodeGen tests use the aliases. Additionally, for the f and d instructions with rounding mode, the tests for the aliased versions are moved and tightened such that they can actually detect if alias emission is enabled. (see D40902 for context) Differential Revision: https://reviews.llvm.org/D41225 Patch by Mario Werner. llvm-svn: 320797
* [RISCV] Implement floating point assembler pseudo instructionsAlex Bradbury2017-12-131-0/+77
Adds the assembler aliases for the floating point instructions which can be mapped to a single canonical instruction. The missing pseudo instructions (flw, fld, fsw, fsd) are marked as TODO. Other things, like for example PCREL_LO, have to be implemented first. This patch builds upon D40902. Differential Revision: https://reviews.llvm.org/D41071 Patch by Mario Werner. llvm-svn: 320569
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