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path: root/llvm/test/MC/RISCV/rv32i-invalid.s
Commit message (Expand)AuthorAgeFilesLines
* [RISCV] Fix disassembling of fence instruction with invalid fieldAna Pazos2018-10-111-0/+1
* [RISCV] Support named operands for CSR instructions.Ana Pazos2018-10-041-0/+10
* [RISCV][MC] Improve parsing of jal/j operandsAlex Bradbury2018-09-201-2/+0
* [RISCV][MC] Reject bare symbols for the simm12 operand typeAlex Bradbury2018-09-181-7/+8
* [RISCV][MC] Tighten up checking of sybol operands to lui and auipcAlex Bradbury2018-09-181-5/+18
* [RISCV] Fixed SmallVector.h Assertion `idx < size()'Ana Pazos2018-08-301-0/+2
* [RISCV] Add InstAlias definitions for add[w], and, xor, or, sll[w], srl[w], s...Alex Bradbury2018-08-081-1/+1
* [RISCV] Implement MC layer support for the fence.tso instructionAlex Bradbury2018-06-081-0/+3
* [RISCV] Add support for %pcrel_lo.Ahmed Charles2018-02-061-0/+9
* [RISCV] MC layer support for the standard RV64I instructionsAlex Bradbury2017-12-071-2/+2
* [RISCV] MC layer support for the standard RV32F instruction set extensionAlex Bradbury2017-12-071-0/+4
* [RISCV] MC layer support for the standard RV32A instruction set extensionAlex Bradbury2017-11-091-0/+2
* [RISCV] MC layer support for the standard RV32M instruction set extensionAlex Bradbury2017-11-091-0/+3
* [RISCV] RISCVAsmParser: early exit if RISCVOperand isn't immediate as expectedAlex Bradbury2017-10-191-0/+3
* [RISCV] Add common fixups and relocationsAlex Bradbury2017-09-281-4/+57
* [RISCV] Add support for all RV32I instructionsAlex Bradbury2017-09-171-3/+47
* [RISCV] Add RISCVInstPrinter and basic MC assembler testsAlex Bradbury2017-08-151-0/+30
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