| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Complete the SPE instruction set patterns | Justin Hibbits | 2018-07-18 | 1 | -3/+157 |
| | | | | | | | | | | This is the lead-up to having SPE codegen. Add the rest of the instructions, along with MC tests. Differential Revision: https://reviews.llvm.org/D44829 llvm-svn: 337346 | ||||
| * | Add support for SPE load/store from memory. | Joerg Sonnenberger | 2014-08-08 | 1 | -0/+157 |
| | | | | | llvm-svn: 215220 | ||||
| * | Add the majority of the remaining SPE instructions. | Joerg Sonnenberger | 2014-08-07 | 1 | -0/+415 |
| | | | | | llvm-svn: 215131 | ||||
| * | Indent | Joerg Sonnenberger | 2014-08-07 | 1 | -15/+15 |
| | | | | | llvm-svn: 215126 | ||||
| * | Add first bunch of SPE instructions. As they overlap with Altivec, mark | Joerg Sonnenberger | 2014-08-07 | 1 | -0/+50 |
| them as parser-only until the disassembler is extended to handle predicates properly. llvm-svn: 215102 | |||||
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index : bcm5719-llvm | |
| Project Ortega BCM5719 LLVM | Raptor Computing Systems |
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