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* Support for microMIPS jump instructionsZoran Jovanovic2013-10-293-0/+89
| | | | llvm-svn: 193623
* Added tests for microMIPS relocations 1.Zoran Jovanovic2013-10-243-0/+191
| | | | llvm-svn: 193332
* [mips][msa] Direct Object Emission support for the LSA instruction.Matheus Almeida2013-10-231-0/+9
| | | | llvm-svn: 193240
* [mips][msa] Direct Object Emission support for conditional branches.Matheus Almeida2013-10-221-0/+78
| | | | | | | | | | | | These branches have a 16-bit offset (R_MIPS_PC16). List of conditional branch instructions: bnz.{b,h,w,d} bnz.v bz.{b,h,w,d} bz.v llvm-svn: 193157
* [mips][msa] Direct Object Emission support for LD/ST instructions.Matheus Almeida2013-10-211-0/+30
| | | | llvm-svn: 193082
* [mips][msa] Direct Object Emission support for LDI instructions.Matheus Almeida2013-10-211-0/+19
| | | | llvm-svn: 193081
* [mips][msa] Direct Object Emission support for MOVE.v.Matheus Almeida2013-10-211-0/+3
| | | | llvm-svn: 193080
* [mips][msa] Direct Object Emission support for CTCMSA and CFCMSA. Matheus Almeida2013-10-211-0/+105
| | | | | | | | These instructions are logically related as they allow read/write of MSA control registers. Currently MSA control registers are emitted by number but hopefully that will change as soon as GAS starts accepting them by name as that would make the assembly easier to read. llvm-svn: 193078
* [mips][msa] Direct Object Emission of SPLAT instruction.Matheus Almeida2013-10-211-0/+12
| | | | llvm-svn: 193077
* [mips][msa] Fix definition of SLD instruction.Matheus Almeida2013-10-211-12/+12
| | | | | | | The second parameter of the SLD intrinsic is the number of columns (GPR) to slide left the source array. llvm-svn: 193076
* [mips] Set HI/LO registers' HWEncoding field.Akira Hatanaka2013-10-151-0/+31
| | | | llvm-svn: 192661
* [mips][msa] Direct Object Emission support for BIT instructions.Matheus Almeida2013-10-141-0/+150
| | | | | | | | | | | | | | | | | | List of instructions: bclri.{b,h,w,d} binsli.{b,h,w,d} binsri.{b,h,w,d} bnegi.{b,h,w,d} bseti.{b,h,w,d} sat_s.{b,h,w,d} sat_u.{b,h,w,d} slli.{b,h,w,d} srai.{b,h,w,d} srari.{b,h,w,d} srli.{b,h,w,d} srlri.{b,h,w,d} llvm-svn: 192589
* [mips][msa] Direct Object Emission support for VEC instructions.Matheus Almeida2013-10-141-0/+27
| | | | | | | List of instructions: and.v, bmnz.v, bmz.v, bsel.v, nor.v, or.v, xor.v. llvm-svn: 192588
* [mips][msa] Direct Object Emission of INSVE.{b,h,w,d}.Matheus Almeida2013-10-141-0/+18
| | | | llvm-svn: 192587
* [mips][msa] Direct Object Emission for the majority of the ELM instructions.Matheus Almeida2013-10-141-0/+48
| | | | | | | | | | List of instructions: copy_s.{b,h,w} copy_u.{b,h,w} sldi.{b,h,w,d} splati.{b,h,w,d} llvm-svn: 192586
* [mips][msa] Direct Object Emission of INSERT.{B,H,W} instruction.Matheus Almeida2013-10-141-0/+15
| | | | | | | | | INSERT is the first type of MSA instruction that requires a change to the way MSA registers are parsed. This happens because MSA registers may be suffixed by an index in the form of an immediate or a general purpose register. The changes to parseMSARegs reflect that requirement. llvm-svn: 192582
* This reverts 192447 because of compiler warning generated on darwin build.Matheus Almeida2013-10-111-15/+0
| | | | llvm-svn: 192451
* This reverts r192449 because of compiler warning generated on darwin build.Matheus Almeida2013-10-111-48/+0
| | | | llvm-svn: 192450
* [mips][msa] Direct Object Emission for the majority of the ELM instructions.Matheus Almeida2013-10-111-0/+48
| | | | llvm-svn: 192449
* [mips][msa] Direct Object Emission of INSERT.{B,H,W} instruction.Matheus Almeida2013-10-111-0/+15
| | | | | | | | INSERT is the first type of MSA instruction that requires a change to the way MSA registers are parsed. This happens because MSA registers may be suffixed by an index in the form of an immediate or a general purpose register. The changes to parseMSARegs reflect that requirement. llvm-svn: 192447
* Remove some really nasty uses of hasRawTextSupport.Rafael Espindola2013-10-054-26/+43
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When MC was first added, targets could use hasRawTextSupport to keep features working before they were added to the MC interface. The design goal of MC is to provide an uniform api for printing assembly and object files. Short of relaxations and other corner cases, a object file is just another representation of the assembly. It was never the intention that targets would keep doing things like if (hasRawTextSupport()) Set flags in one way. else Set flags in another way. When they do that they create two code paths and the object file is no longer just another representation of the assembly. This also then requires testing with llc -filetype=obj, which is extremelly brittle. This patch removes some of these hacks by replacing them with smaller ones. The ARM flag setting is trivial, so I just moved it to the constructor. For Mips, the patch adds two temporary hack directives that allow the assembly to represent the same things as the object file was already able to. The hope is that the mips developers will replace the hack directives with the same ones that gas uses and drop the -print-hack-directives flag. I will also try to implement a target streamer interface, so that we can move this out of the common code. In summary, for any new work, two rules of the thumb are * Don't use "llc -filetype=obj" in tests. * Don't add calls to hasRawTextSupport. llvm-svn: 192035
* reverting per requestJack Carter2013-10-041-6/+1
| | | | llvm-svn: 191992
* [MC][AsmParser] Hook for post assembly file processingJack Carter2013-10-041-1/+6
| | | | | | | | | | | | | | | | | | | | | This patch handles LLVM standalone assembler (llvm-mc) ELF flag setting based on input file directive processing. Mips assembly requires processing inline directives that directly and indirectly affect the output ELF header flags. This patch handles one ".abicalls". To process these directives we are following the model the code generator uses by storing state in a container as we go through processing and when we detect the end of input file processing, AsmParser is notified and we update the ELF header flags through a MipsELFStreamer method with a call from MCTargetAsmParser::emitEndOfAsmFile(MCStreamer &OutStreamer). This patch will allow other targets the same functionality. Jack llvm-svn: 191982
* This patch adds aliases for Mips sub instruction with immediate operands. ↵Vladimir Medic2013-10-011-0/+4
| | | | | | Corresponding test cases are added. llvm-svn: 191734
* [mips][msa] Direct Object Emission for I8 instructions.Jack Carter2013-09-301-0/+36
| | | | | | | | | This patch adds Direct Object Emission support for I8 instructions: andi.b, bmnzi.b, bmzi.b, bseli.b, nori.b, ori.b, shf.{b,h,w} and xori.b. Patch by Matheus Almeida llvm-svn: 191688
* [mips][msa] Direct Object Emission for I5 instructions.Jack Carter2013-09-301-0/+138
| | | | | | | | | This patch adds Direct Object Emission support for I5 instructions: addvi.{b,h,w,d}, ceqi.{b,h,w,d}, clei_s.{b,h,w,d}, clei_u.{b,h,w,d}, clti_s.{b,h,w,d}, clti_u.{b,h,w,d}, maxi_s.{b,h,w,d}, maxi_u.{b,h,w,d}, mini_s.{b,h,w,d}, mini_u.{b,h,w,d}, subvi.{b,h,w,d}. Patch by Matheus Almeida llvm-svn: 191687
* [mips][msa] Direct Object Emission for 2R instructions.Jack Carter2013-09-301-0/+36
| | | | | | | | | This patch adds Direct Object Emission support for 2R instructions: nloc.{b,h,w}, nlzc.{b,h,w}, pcnt.{b,w,d}. Patch by Matheus Almeida llvm-svn: 191685
* [PATCH 1/4] [mips][msa] Source register of FILL instructions is GPRJack Carter2013-09-301-0/+15
| | | | | | | | and not an MSA register Patch by Matheus Almeida llvm-svn: 191684
* [mips][msa] Direct Object Emission for 3RF instructions.Jack Carter2013-09-261-0/+252
| | | | | | Patch by Matheus Almeida llvm-svn: 191461
* [mips][msa] Direct Object Emission for 3R instructions.Jack Carter2013-09-261-0/+720
| | | | | | | | This is the first set of instructions with a ".b" modifier thus we need to add the required code to disassemble a MSA128B register class. Patch by Matheus Almeida llvm-svn: 191415
* [mips][msa] Direct Object Emission for 2RF instructions.Jack Carter2013-09-251-0/+90
| | | | | | Patch by Matheus Almeida llvm-svn: 191413
* [mips][msa] Direct Object Emission support for the MSA instruction set. Jack Carter2013-09-251-0/+12
| | | | | | | | | | In more detail, this patch adds the ability to parse, encode and decode MSA registers ($w0-$w31). The format of 2RF instructions (MipsMSAInstrFormat.td) was updated so that we could attach a test case to this patch i.e., the test case parses, encodes and decodes 2 MSA instructions. Following patches will add the remainder of the instructions. Note that DecodeMSA128BRegisterClass is missing from MipsDisassembler.td because it's not yet required at this stage and having it would cause a compiler warning (unused function). Patch by Matheus Almeida llvm-svn: 191412
* This patch implements Mips load/store instructions from/to coprocessor 2. ↵Vladimir Medic2013-09-161-0/+8
| | | | | | Test cases are added. llvm-svn: 190780
* Fixed bug when generating Load Upper Immediate microMIPS instruction.Zoran Jovanovic2013-09-141-0/+3
| | | | llvm-svn: 190746
* Support for microMIPS DIV instructions.Zoran Jovanovic2013-09-141-0/+6
| | | | llvm-svn: 190745
* Add test cases for Mips mthc1/mfhc1 instructions. Add check for odd value of ↵Vladimir Medic2013-09-101-0/+4
| | | | | | register when PFU is 32 bit. llvm-svn: 190397
* [mips] Add definition of instruction "drotr32" (double rotate right plus 32).Akira Hatanaka2013-09-071-1/+5
| | | | llvm-svn: 190232
* [mips] Set instruction itineraries of loads, stores and conditional moves.Akira Hatanaka2013-09-061-2/+2
| | | | llvm-svn: 190219
* This patch adds support for microMIPS Multiply and Add/Sub instructions. ↵Vladimir Medic2013-09-061-0/+26
| | | | | | Test cases are included in patch. llvm-svn: 190154
* This patch adds support for microMIPS Move Conditional instructions. Test ↵Vladimir Medic2013-09-061-0/+26
| | | | | | cases are included in patch. llvm-svn: 190148
* [mips] Use ptr_rc to simplify definitions of base+index load/store instructions.Akira Hatanaka2013-08-283-2/+21
| | | | | | Also, fix predicates. llvm-svn: 189432
* This patch implements trap instructions for mips. The test cases are added.Vladimir Medic2013-08-261-2/+58
| | | | llvm-svn: 189213
* [micromips] Print instruction alias "not" if the last operand of a nor is zero.Akira Hatanaka2013-08-211-2/+2
| | | | llvm-svn: 188851
* [mips] Guard micromips instructions with predicate InMicroMips. Also, fixAkira Hatanaka2013-08-201-2/+2
| | | | | | assembler predicate HasStdEnd so that it is false when the target is micromips. llvm-svn: 188824
* [mips] Fix instruction definitions that were incorrectly marked as ↵Akira Hatanaka2013-08-191-0/+1
| | | | | | code-gen-only. llvm-svn: 188690
* This patch implements wait instruction for mips. Examples are added in test ↵Vladimir Medic2013-08-161-0/+4
| | | | | | files. llvm-svn: 188537
* [tests] Cleanup initialization of test suffixes.Daniel Dunbar2013-08-161-2/+0
| | | | | | | | | | | | | | | | | - Instead of setting the suffixes in a bunch of places, just set one master list in the top-level config. We now only modify the suffix list in a few suites that have one particular unique suffix (.ml, .mc, .yaml, .td, .py). - Aside from removing the need for a bunch of lit.local.cfg files, this enables 4 tests that were inadvertently being skipped (one in Transforms/BranchFolding, a .s file each in DebugInfo/AArch64 and CodeGen/PowerPC, and one in CodeGen/SI which is now failing and has been XFAILED). - This commit also fixes a bunch of config files to use config.root instead of older copy-pasted code. llvm-svn: 188513
* [mips] Fix bug in parsing accumulator registers.Akira Hatanaka2013-08-141-0/+14
| | | | llvm-svn: 188344
* [Mips] Support for unaligned load/store microMips instructionsJack Carter2013-08-131-0/+26
| | | | | | | | This includes instructions lwl, lwr, swl and swr. Patch by Zoran Jovnovic llvm-svn: 188312
* This patch implements ei and di instructions for mips. Test cases are added.Vladimir Medic2013-08-121-1/+19
| | | | llvm-svn: 188176
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