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* [mips] Rewrite MipsAsmParser and MipsOperand.Daniel Sanders2014-03-3115-53/+65
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Highlights: - Registers are resolved much later (by the render method). Prior to that point, GPR32's/GPR64's are GPR's regardless of register size. Similarly FGR32's/FGR64's/AFGR64's are FGR's regardless of register size or FR mode. Numeric registers can be anything. - All registers are parsed the same way everywhere (even when handling symbol aliasing) - One consequence is that all registers can be specified numerically almost anywhere (e.g. $fccX, $wX). The exception is symbol aliasing but that can be easily resolved. - Removes the need for the hasConsumedDollar hack - Parenthesis and Bracket suffixes are handled generically - Micromips instructions are parsed directly instead of going through the standard encodings first. - rdhwr accepts all 32 registers, and the following instructions that previously xfailed now work: ddiv, ddivu, div, divu, cvt.l.[ds], se[bh], wsbh, floor.w.[ds], c.ngl.d, c.sf.s, dsbh, dshd, madd.s, msub.s, nmadd.s, nmsub.s, swxc1 - Diagnostics involving registers point at the correct character (the $) - There's only one kind of immediate in MipsOperand. LSA immediates are handled by the predicate and renderer. Lowlights: - Hardcoded '$zero' in the div patterns is handled with a hack. MipsOperand::isReg() will return true for a k_RegisterIndex token with Index == 0 and getReg() will return ZERO for this case. Note that it doesn't return ZERO_64 on isGP64() targets. - I haven't cleaned up all of the now-unused functions. Some more of the generic parser could be removed too (integers and relocs for example). - insve.df needed a custom decoder to handle the implicit fourth operand that was needed to make it parse correctly. The difficulty was that the matcher expected a Token<'0'> but gets an Imm<0>. Adding an implicit zero solved this. Reviewers: matheusalmeida, vmedic Reviewed By: matheusalmeida Differential Revision: http://llvm-reviews.chandlerc.com/D3222 llvm-svn: 205229
* [mips] Implement missing relocations in the integrated assembler.Daniel Sanders2014-03-311-4/+1
| | | | | | | | | | %got_hi, %got_lo, %call_hi, %call_lo, %higher, and %highest are now recognised by MipsAsmParser::getVariantKind(). To prevent future issues with missing entries in this StringSwitch, I've added an assertion to the default case. llvm-svn: 205200
* [mips] Remove R_MIPS_GOT which isn't used and shares the same number as ↵Daniel Sanders2014-03-311-1/+1
| | | | | | | | | R_MIPS_GOT16 Unlike my previous commit, don't try to remove the corresponding VK_Mips_GOT yet even though it shares the same assembly text since that is used. llvm-svn: 205196
* Revert r205194 - [mips] Removed R_MIPS_GOT. It's identical to R_MIPS_GOT16.Daniel Sanders2014-03-311-1/+1
| | | | | | There's a couple additional bits I missed. llvm-svn: 205195
* [mips] Removed R_MIPS_GOT. It's identical to R_MIPS_GOT16.Daniel Sanders2014-03-311-1/+1
| | | | llvm-svn: 205194
* llvm/test/MC/Mips/mips64r2/valid-xfail.s: This REQUIRES asserts. Seems it ↵NAKAMURA Takumi2014-03-311-0/+1
| | | | | | doesn't fail with -Asserts. llvm-svn: 205182
* [mips] Added a full set of instruction test cases for all ISA's (but not ASE's).Daniel Sanders2014-03-3118-0/+2280
| | | | | | | | | | | | | | | | | | | Summary: Where those ISA's are not currently supported, the test is run with the smallest superset of that ISA. Some instructions are valid but don't pass yet. These have been placed in the valid-xfail.s's which will XPASS if _any_ instruction starts working. The valid.s's do not verify the encoding yet. There are also no tests checking that instructions from neighbouring ISA's are not accepted. Reviewers: matheusalmeida Reviewed By: matheusalmeida Differential Revision: http://llvm-reviews.chandlerc.com/D3214 llvm-svn: 205180
* Convert one last llc -filetype=obj test.Rafael Espindola2014-03-282-29/+70
| | | | | | Unfortunately this one fails deep inside the mips backend, so xfail it. llvm-svn: 205042
* Convert llc -filetype=obj test.Rafael Espindola2014-03-282-19/+65
| | | | llvm-svn: 205040
* Convert llc -filetype=obj test.Rafael Espindola2014-03-282-33/+70
| | | | llvm-svn: 205039
* Remove bogus test.Rafael Espindola2014-03-281-18/+0
| | | | | | | | | It was using "lc -filetype=obj" just to pass the result to "llvm-objdupm -disassemble" and then filecheck assembly. The CHECK-NOT would never match anyway since it was missing $. llvm-svn: 205036
* Convert another llc -filetype=obj test.Rafael Espindola2014-03-282-40/+134
| | | | llvm-svn: 205033
* Map ELf flags back to more specific section kinds.Rafael Espindola2014-03-282-39/+87
| | | | | | With that, convert another llc -filetype=obj test. llvm-svn: 205031
* Parse .gpdword and convert another llc -filetype=obj test.Rafael Espindola2014-03-283-44/+87
| | | | llvm-svn: 205028
* convert another llc -filetype=obj test.Rafael Espindola2014-03-282-26/+64
| | | | llvm-svn: 205027
* Convert "llc -filetype=obj" test into llvm-mc tests.Rafael Espindola2014-03-284-39/+234
| | | | llvm-svn: 205026
* [mips] Attempting to use register $32 should be an error instead of an ↵Daniel Sanders2014-03-271-0/+8
| | | | | | | | | | | | assertion. Reviewers: matheusalmeida Reviewed By: matheusalmeida Differential Revision: http://llvm-reviews.chandlerc.com/D3201 llvm-svn: 204932
* [mips] Add support for .cpsetupDaniel Sanders2014-03-271-0/+36
| | | | | | | | | | | | | | Summary: Patch by Robert N. M. Watson His work was sponsored by: DARPA, AFRL Small corrections by myself. CC: theraven, matheusalmeida Differential Revision: http://llvm-reviews.chandlerc.com/D3199 llvm-svn: 204924
* [mips] Use TwoOperandAliasConstraint for ArithLogicR instructions.Matheus Almeida2014-03-263-0/+16
| | | | | | | | This enables TableGen to generate an additional two operand matcher for our ArithLogicR class of instructions (constituted by 3 register operands). E.g.: and $1, $2 <=> and $1, $1, $2 llvm-svn: 204826
* [mips] Add support to the '.dword' directive.Matheus Almeida2014-03-261-0/+36
| | | | | | | The '.dword' directive accepts a list of expressions and emits them in 8-byte chunks in successive locations. llvm-svn: 204822
* [mips] Add support to '.set mips64'.Matheus Almeida2014-03-261-0/+5
| | | | | | | | | | The '.set mips64' directive enables the feature Mips:FeatureMips64 from assembly. Note that it doesn't modify the ELF header as opposed to the use of -mips64 from the command-line. The reason for this is that we want to be as compatible as possible with existing assemblers like GAS. llvm-svn: 204817
* [mips] Add support to '.set mips64r2'.Matheus Almeida2014-03-261-0/+5
| | | | | | | | | | The '.set mips64r2' directive enables the feature Mips:FeatureMips64r2 from assembly. Note that it doesn't modify the ELF header as opposed to the use of -mips64r2 from the command-line. The reason for this is that we want to be as compatible as possible with existing assemblers like GAS. llvm-svn: 204815
* [mips] Add support for '.option pic2'.Matheus Almeida2014-03-262-0/+16
| | | | | | | | | The directive '.option pic2' enables PIC from assembly source. At the moment none of the macros/directives check the PIC bit but that's going to be fixed relatively soon. For example, the expansion of macros like 'la' depend on the relocation model. llvm-svn: 204803
* [mips] Add tests for t0-t3 for N32/N64Daniel Sanders2014-03-261-33/+40
| | | | | | | These are aliases of t4-t7 and are provided for compatibility with both the original ABI documentation (using t4-t7) and GNU As (using t0-t3) llvm-svn: 204797
* [mips] The register names depend on the ABI being N32/N64 rather than the ↵Daniel Sanders2014-03-263-1/+46
| | | | | | | | | | | | | | arch being mips64 Summary: Added test cases for O32 and N32 on MIPS64. Reviewers: matheusalmeida Reviewed By: matheusalmeida Differential Revision: http://llvm-reviews.chandlerc.com/D3175 llvm-svn: 204796
* [mips] $s8 is an alias for $fp in all ABI's, not just N32/N64.Daniel Sanders2014-03-262-1/+2
| | | | llvm-svn: 204793
* [mips] Move the CHECK lines in mips*-register-names.s to make it more ↵Daniel Sanders2014-03-262-128/+64
| | | | | | | | | obvious which CHECK matches with which insn This reveals a small mistake in mips-register-names.s ($sp is tested twice and $s8 is not tested) which will be fixed in a follow-up commit. llvm-svn: 204792
* [mips] '.set at=$0' should be equivalent to '.set noat'Daniel Sanders2014-03-252-4/+14
| | | | | | Differential Revision: http://llvm-reviews.chandlerc.com/D3171 llvm-svn: 204714
* [mips] Correct testcase for .set at=$reg and emit the new warnings for ↵Daniel Sanders2014-03-252-94/+163
| | | | | | | | | | | | | | | | | | numeric registers too. Summary: Remove the XFAIL added in my previous commit and correct the test such that it correctly tests the expansion of the assembler temporary. Also added a test to check that $at is always $1 when written by the user. Corrected the new assembler temporary warnings so that they are emitted for numeric registers too. Differential Revision: http://llvm-reviews.chandlerc.com/D3169 llvm-svn: 204711
* [mips] Fix assembler temporary expansion and add associated warnings about ↵Daniel Sanders2014-03-251-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | the use of $at. Summary: The assembler temporary is normally $at ($1) but can be reassigned using '.set at=$reg'. Regardless of which register is nominated as the assembler temporary, $at remains $1 when written by the user. Adds warnings under the following conditions: * The register nominated as the assembler temporary is used by the user. * '.set noat' is in effect and $at is used by the user. Both of these only work for named registers. I have a follow up commit that makes it work for numeric registers as well. XFAIL set-at-directive.s since it incorrectly tests that $at is redefined by '.set at=$reg'. Testcases will follow in a separate commit. Patch by David Chisnall His work was sponsored by: DARPA, AFRL Differential Revision: http://llvm-reviews.chandlerc.com/D3167 llvm-svn: 204710
* [mips] Add error message when trying to use $at in '.set noat' mode.Daniel Sanders2014-03-241-0/+27
| | | | | | | | | | Summary: Patch by David Chisnall His work was sponsored by: DARPA, AFRL Differential Revision: http://llvm-reviews.chandlerc.com/D3158 llvm-svn: 204621
* [mips] Add regression tests for parenthetic expressions in MIPS assembly.Daniel Sanders2014-03-241-0/+12
| | | | | | | | | | | | Summary: These expressions already worked but weren't tested. Patch by Robert N. M. Watson and David Chisnall (it was originally two patches) Their work was sponsored by: DARPA, AFRL Differential Revision: http://llvm-reviews.chandlerc.com/D3156 llvm-svn: 204612
* [mips] Allow dsubu to take an immediate as an alias for dsubiu.Daniel Sanders2014-03-241-0/+2
| | | | | | | | | | Summary: Patch by David Chisnall His work was sponsored by: DARPA, AFRL Differential Revision: http://llvm-reviews.chandlerc.com/D3155 llvm-svn: 204611
* [mips] Implement shorthand add / sub forms for MIPS.Daniel Sanders2014-03-242-0/+44
| | | | | | | | | | | | | | | | | | | | | Summary: - If only two registers are passed to a three-register operation, then the first argument is both source and destination register. - If a non-register is passed as the last argument, generate the immediate version of the instruction. Also mark DADD commutative and add scheduling information (to the generic scheduler), and implement DSUB. Patch by David Chisnall His work was sponsored by: DARPA, AFRL CC: theraven Differential Revision: http://llvm-reviews.chandlerc.com/D3148 llvm-svn: 204605
* [MIPS] Add cpu octeon and some instructionsKai Nacke2014-03-201-0/+23
| | | | | | | | | | The Octeon cpu from Cavium Networks is mips64r2 based and has an extended instruction set. In order to utilize this with LLVM, a new cpu feature "octeon" and a subtarget feature "cnmips" is added. A small set of new instructions (baddu, dmul, pop, dpop, seq, sne) is also added. LLVM generates dmul, pop and dpop instructions with option -mcpu=octeon or -mattr=+cnmips. llvm-svn: 204337
* Provide an operand for microMIPS wait instruction.Zoran Jovanovic2014-03-201-0/+3
| | | | llvm-svn: 204329
* Implementation of microMIPS 16-bit instructions MOVE and JALR.Zoran Jovanovic2014-03-203-5/+24
| | | | | | Differential Revision: http://llvm-reviews.chandlerc.com/D3112 llvm-svn: 204325
* Mark alias symbols as microMIPS if necessary. Differential Revision: ↵Zoran Jovanovic2014-03-201-0/+16
| | | | | | http://llvm-reviews.chandlerc.com/D3080 llvm-svn: 204323
* [mips] Making sure that a '.set noreorder' directive is correctly parsedMatheus Almeida2014-03-191-0/+5
| | | | | | and emitted and that no NOPs are emitted in a 'noreorder section'. llvm-svn: 204250
* [mips] Implement NaCl sandboxing of function calls:Sasa Stankovic2014-03-111-0/+66
| | | | | | | | | * Add masking instructions before indirect calls (in MC layer). * Align call + branch delay to the bundle end (in MC layer). Differential Revision: http://llvm-reviews.chandlerc.com/D3032 llvm-svn: 203606
* [mips] Implement NaCl sandboxing of loads, stores and SP changes:Sasa Stankovic2014-03-101-0/+191
| | | | | | | | | | * Add masking instructions before loads and stores (in MC layer). * Add masking instructions after SP changes (in MC layer). * Forbid loads, stores and SP changes in delay slots (in MI layer). Differential Revision: http://llvm-reviews.chandlerc.com/D2904 llvm-svn: 203484
* [mips] Assembly parser must invoke the target streamer to handle .set ↵Matheus Almeida2014-03-101-0/+1
| | | | | | reorder macro. llvm-svn: 203459
* Moved test file from test/MC/Mips to test/CodeGen/Mips.Sasa Stankovic2014-03-071-96/+0
| | | | llvm-svn: 203298
* This patch implements .set dsp directive and sets appropriate feature ↵Vladimir Medic2014-03-051-0/+7
| | | | | | bits.This directive is a counterpart of -mattr=dsp command line option with the exception that it does not influence elf header flags. The usage example is gives in test file. llvm-svn: 202966
* This patch implements .set mips32r2 directive and sets appropriate feature ↵Vladimir Medic2014-03-041-1/+10
| | | | | | bits. It also introduces helper functions that are used to set and clear feature bits as necessary. This directive is a counterpart of -mips32r2 command line options with the exception that it does not influence elf header flags. The usage example is gives in test file. llvm-svn: 202807
* [mips] support FK_Data_2 and FK_Data_8 to fix big-endian debug dataEd Maste2014-03-031-0/+43
| | | | | | | | | This fixes invalid lengths in .debug_aranges on big-endian mips64 (lengths appear to be left-shifted by 32 bits) and in .debug_loc. Differential Revision: http://llvm-reviews.chandlerc.com/D2517 llvm-svn: 202716
* This patch implements jalx instruction for Mips architecture.This ↵Vladimir Medic2014-03-031-1/+11
| | | | | | instruction executes a procedure call within the current 256 MB-aligned region and change the ISA Mode from MIPS32 to microMIPS32 or MIPS16e. Usage samples for assembler and dissasembler are provided as well. llvm-svn: 202706
* Add missing FileCheck in test command line.Sasa Stankovic2014-03-011-1/+1
| | | | llvm-svn: 202594
* Fixed encoding of SYSCALL microMIPS instruction.Zoran Jovanovic2014-02-281-5/+5
| | | | llvm-svn: 202523
* Revert revision 202518 because of wrong commit message.Zoran Jovanovic2014-02-281-5/+5
| | | | llvm-svn: 202521
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