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* [mips][mips64r6] bc2[ft] are not available on MIPS32r6/MIPS64r6Daniel Sanders2014-06-124-0/+28
| | | | | | | | | | | | | | | | Summary: These instructions are not implemented for any MIPS ISA so we only need testcases. Depends on D4110 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D4111 llvm-svn: 210786
* [mips][mips64r6] [sl][duw]xc1 are not available on MIPS32r6/MIPS64r6Daniel Sanders2014-06-124-0/+40
| | | | | | | | | | | | | | | | | Summary: Folded mips64-fp-indexed-ls.ll into fp-indexed-ls.ll. To do so, the zext's in mips64-fp-indexed-ls.ll were changed to implicit sign extensions (performed by getelementptr). This does not affect the purpose of the test. Depends on D4004 Reviewers: zoran.jovanovic, jkolek, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D4110 llvm-svn: 210784
* [mips][mips64r6] prefx is not available on MIPS32r6/MIPS64r6Daniel Sanders2014-06-122-0/+42
| | | | | | | | | | | | Summary: We haven't implemented this instruction so we only add a test case. Reviewers: vmedic, zoran.jovanovic, jkolek Reviewed By: jkolek Differential Revision: http://reviews.llvm.org/D4004 llvm-svn: 210779
* [mips][mips64r6] c.cond.fmt, mov[fntz], and mov[fntz].[ds] are not available ↵Daniel Sanders2014-06-124-0/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | on MIPS32r6/MIPS64r6 Summary: c.cond.fmt has been replaced by cmp.cond.fmt. Where c.cond.fmt wrote to dedicated condition registers, cmp.cond.fmt writes 1 or 0 to normal FGR's (like the GPR comparisons). mov[fntz] have been replaced by seleqz and selnez. These instructions conditionally zero a register based on a bool in a GPR. The results can then be or'd together to act as a select without, for example, requiring a third register read port. mov[fntz].[ds] have been replaced with sel.[ds] MIPS64r6 currently generates unnecessary sign-extensions for most selects. This is because the result of a SETCC is currently an i32. Bits 32-63 are undefined in i32 and the behaviour of seleqz/selnez would otherwise depend on undefined bits. Later, we will fix this by making the result of SETCC an i64 on MIPS64 targets. Depends on D3958 Reviewers: jkolek, vmedic, zoran.jovanovic Reviewed By: vmedic, zoran.jovanovic Differential Revision: http://reviews.llvm.org/D4003 llvm-svn: 210777
* [mips][mips64r6] jalx is not available on MIPS32r6/MIPS64r6Daniel Sanders2014-06-121-0/+31
| | | | | | | | | | | | Summary: Depends on D3957 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3958 llvm-svn: 210775
* [mips][mips64r6] Add R_MIPS_PC19_S2Zoran Jovanovic2014-06-122-11/+41
| | | | | | Differential Revision: http://reviews.llvm.org/D3866 llvm-svn: 210773
* [mips][mips64r6] Add bgec and bgeuc instructionsZoran Jovanovic2014-06-122-0/+4
| | | | | | Differential Revision: http://reviews.llvm.org/D4017 llvm-svn: 210770
* [mips][mips64r6] madd.[ds], msub.[ds], nmadd.[ds], and nmsub.[ds] are not ↵Daniel Sanders2014-06-121-0/+15
| | | | | | | | | | | | | | | | | | | | available on MIPS32r6/MIPS64r6 Summary: This patch updates both the assembler and the code generator. MIPS32r6/MIPS64r6 replaces them with maddf.[ds] and msubf.[ds] which are fused multiply-add/sub operations. We don't emit these yet, this patch only prevents the removed instructions from being emitted. Depends on D3955 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3956 llvm-svn: 210763
* [mips][mips64r6] madd/maddu/msub/msubu are not available on MIPS32r6/MIPS64r6Daniel Sanders2014-06-121-0/+13
| | | | | | | | | | | | | | | | Summary: This patch disables madd/maddu/msub/msubu in both the assembler and code generator. Depends on D3896 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3955 llvm-svn: 210762
* [mips][mips64r6] Replace m[tf]hi, m[tf]lo, mult, multu, dmult, dmultu, div, ↵Daniel Sanders2014-06-127-2/+66
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ddiv, divu, ddivu for MIPS32r6/MIPS64. Summary: The accumulator-based (HI/LO) multiplies and divides from earlier ISA's have been removed and replaced with GPR-based equivalents. For example: div $1, $2 mflo $3 is now: div $3, $1, $2 This patch disables the accumulator-based multiplies and divides for MIPS32r6/MIPS64r6 and uses the GPR-based equivalents instead. Renamed expandPseudoDiv to insertDivByZeroTrap to better describe the behaviour of the function. MipsDelaySlotFiller now invalidates the liveness information when moving instructions to the delay slot. Without this, divrem.ll will abort since %GP ends up used before it is defined. Reviewers: vmedic, zoran.jovanovic, jkolek Reviewed By: jkolek Differential Revision: http://reviews.llvm.org/D3896 llvm-svn: 210760
* [mips] Move CHECK lines to the same line as the instruction it's testingMatheus Almeida2014-06-122-8/+4
| | | | | | | | for consistency with the other tests. No functional changes. llvm-svn: 210757
* [mips] Implement jr.hb and jalr.hb (Jump Register and Jump and Link Register ↵Matheus Almeida2014-06-1110-0/+62
| | | | | | | | | | | | | | with Hazard Barrier). Summary: These instructions are available in ISAs >= mips32/mips64. For mips32r6/mips64r6, jr.hb has a new encoding format. Reviewers: dsanders Reviewed By: dsanders Differential Revision: http://reviews.llvm.org/D4019 llvm-svn: 210654
* Reduce verbiage of lit.local.cfg filesAlp Toker2014-06-091-2/+1
| | | | | | We can just split targets_to_build in one place and make it immutable. llvm-svn: 210496
* [mips] Fix a bug for NaCl target - Don't report the error when non-dangerousSasa Stankovic2014-06-091-0/+34
| | | | | | | | load/store is in branch delay slot. Differential Revision: http://llvm-reviews.chandlerc.com/D4048 llvm-svn: 210470
* [mips][mips64r6] Add LDPC instructionZoran Jovanovic2014-06-091-0/+1
| | | | | | Differential Revision: http://reviews.llvm.org/D3822 llvm-svn: 210460
* [mips] Fix triple.Matheus Almeida2014-06-052-2/+2
| | | | | | Mips2 is a 32-bit architecture. llvm-svn: 210254
* [mips][mips64r6] Add Relocations R_MIPS_PCHI16, R_MIPS_PCLO16 Zoran Jovanovic2014-05-272-0/+24
| | | | | | Differential Revision: http://reviews.llvm.org/D3860 llvm-svn: 209659
* [mips][mips64r6] Add relocations R_MIPS_PC21_S2, R_MIPS_PC26_S2 Zoran Jovanovic2014-05-272-0/+86
| | | | | | Differential Revision: http://reviews.llvm.org/D3824 llvm-svn: 209655
* [mips] Work around inconsistency in llvm-mc's placement of fixup markersDaniel Sanders2014-05-234-11/+20
| | | | | | | | | | | | | | | | | | | Summary: Add a second fixup table to MipsAsmBackend::getFixupKindInfo() to correctly position llvm-mc's fixup placeholders for big-endian. See PR19836 for full details of the issue. To summarize, the fixup placeholders do not account for endianness properly and the implementations of getFixupKindInfo() for each target are measuring MCFixupKindInfo.TargetOffset from different ends of the instruction encoding to compensate. Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3889 llvm-svn: 209514
* [mips][mips64r6] t(eq|ge|lt|ne)i and t(ge|lt)iu are not available in ↵Daniel Sanders2014-05-233-0/+34
| | | | | | | | | | | | | | MIPS32r6/MIPS64r6 Summary: Depends on D3872 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3891 llvm-svn: 209513
* [mips][mips64r6] [ls][dw][lr] are not available in MIPS32r6/MIPS64r6Daniel Sanders2014-05-234-0/+61
| | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Instead the system is required to provide some means of handling unaligned load/store without special instructions. Options include full hardware support, full trap-and-emulate, and hybrids such as hardware support within a cache line and trap-and-emulate for multi-line accesses. MipsSETargetLowering::allowsUnalignedMemoryAccesses() has been configured to assume that unaligned accesses are 'fast' on the basis that I expect few hardware implementations will opt for pure-software handling of unaligned accesses. The ones that do handle it purely in software can override this. mips64-load-store-left-right.ll has been merged into load-store-left-right.ll The stricter testing revealed a Bits!=Bytes bug in passByValArg(). This has been fixed and the variables renamed to clarify the units they hold. Reviewers: zoran.jovanovic, jkolek, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3872 llvm-svn: 209512
* [mips][mips64r6] addi is not available on MIPS32r6/MIPS64r6Daniel Sanders2014-05-222-0/+16
| | | | | | | | | | | | Summary: Depends on D3787. Tablegen will raise an assertion without it. Reviewers: zoran.jovanovic, jkolek, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3842 llvm-svn: 209419
* [mips][mips64r6] Test that paired single instructions are invalidDaniel Sanders2014-05-221-0/+44
| | | | | | | | | | | | | | Summary: These emit the 'unknown instruction' instead of the correct error because they have not been implemented in LLVM for any MIPS ISA. Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3841 llvm-svn: 209418
* [mips][mips64r6] Add b[on]vcDaniel Sanders2014-05-224-3/+85
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This required me to implement the disassembler for MIPS64r6 since the encodings are ambiguous with other instructions. This in turn revealed a few assembly/disassembly bugs which I have fixed. * da[ht]i only take two operands according to the spec, not three. * DecodeBranchTarget2[16] correctly handles wider immediates than simm16 * Also made non-functional change to DecodeBranchTarget and DecodeBranchTargetMM to keep implementation style consistent between them. * Difficult encodings are handled by a custom decode method on the most general encoding in the group. This method will convert the MCInst to a different opcode if necessary. DecodeBranchTarget is not currently the inverse of getBranchTargetOpValue so disassembling some branch instructions emit incorrect output. This seems to affect branches with delay slots on all MIPS ISA's. I've left this bug for now and temporarily removed the check for the immediate on bc[12]eqz/bc[12]nez in the MIPS32r6/MIPS64r6 tests. jialc and jic crash the disassembler for some reason. I've left these instructions commented out for the moment. Depends on D3760 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3761 llvm-svn: 209415
* [mips][mips64r6] Add bc[12](eq|ne)zDaniel Sanders2014-05-212-0/+16
| | | | | | | | | | | | Summary: Depends on D3691 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3760 llvm-svn: 209292
* Temporarily revert: r209129 - [mips][mips64r6] Sorted *_ENC, *_DESC classes ↵Daniel Sanders2014-05-202-36/+36
| | | | | | | | | | | | and tests After discussion with Zoran, we have decided to temporarily revert this commit. It's causing some difficult to resolve conflicts and we are under time pressure to deliver an initial MIPS64r6 compiler. We will re-apply an equivalent patch once the time pressure has passed. llvm-svn: 209211
* [mips][mips64r6] Sorted *_ENC, *_DESC classes and testsZoran Jovanovic2014-05-192-36/+36
| | | | | | Differential Revision: http://reviews.llvm.org/D3808 llvm-svn: 209129
* [mips][mips64r6] Add SELEQZ and SELNEZ instructionsZoran Jovanovic2014-05-162-0/+4
| | | | | | Differential Revision: http://reviews.llvm.org/D3743 llvm-svn: 208987
* [mips][mips64r6] Add Compact indexed jumps.Zoran Jovanovic2014-05-162-0/+4
| | | | | | Differential Revision: http://reviews.llvm.org/D3707 llvm-svn: 208981
* [mips][mips64r6] Add Compact zero-compare branch-and-link instructionsZoran Jovanovic2014-05-162-0/+12
| | | | | | Differential Revision: http://reviews.llvm.org/D3718 llvm-svn: 208977
* [mips][mips64r6] Add compact branch instructionsZoran Jovanovic2014-05-162-0/+20
| | | | | | Differential Revision: http://reviews.llvm.org/D3691 llvm-svn: 208974
* [mips][mips64r6] Add LWPC and LWUPC instructionsZoran Jovanovic2014-05-162-0/+4
| | | | | | Differential Revision: http://reviews.llvm.org/D3788 llvm-svn: 208971
* [mips][mips64r6] Add Floating Point Compare setting Mask - CMP.condn.fmtZoran Jovanovic2014-05-162-0/+64
| | | | | | Differential Revision: http://reviews.llvm.org/D3750 llvm-svn: 208970
* [mips][mips64r6] Add Floating Point Fused Multiply Add SubtractZoran Jovanovic2014-05-162-0/+8
| | | | | | Differential Revision: http://reviews.llvm.org/D3727 llvm-svn: 208952
* [mips][mips64r6] Add CLASS.fmt instructionsZoran Jovanovic2014-05-152-0/+4
| | | | | | Differential Revision: http://reviews.llvm.org/D3712 llvm-svn: 208894
* [mips][mips64r6] Add RINT.fmt instructionsZoran Jovanovic2014-05-152-0/+4
| | | | | | Differential Revision: http://reviews.llvm.org/D3711 llvm-svn: 208892
* [mips][mips64r6] Add SELEQZ/SELNEZ.fmt instructionsZoran Jovanovic2014-05-152-0/+8
| | | | | | Differential Revision: http://reviews.llvm.org/D3710 llvm-svn: 208891
* [mips][mips64r6] Add MAX/MIN/MAXA/MINA.fmt instructionsZoran Jovanovic2014-05-152-0/+16
| | | | | | Differential Revision: http://reviews.llvm.org/D3709 llvm-svn: 208890
* [mips][mips64r6] Add bitswap, and dbitswapDaniel Sanders2014-05-152-0/+3
| | | | | | | | | | | | Summary: Depends on D3728 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3729 llvm-svn: 208877
* [mips][mips64r6] Add align and dalignDaniel Sanders2014-05-152-0/+3
| | | | | | | | | | | | Summary: Depends on D3689 Reviewers: vmedic, zoran.jovanovic, jkolek Reviewed By: jkolek Differential Revision: http://reviews.llvm.org/D3728 llvm-svn: 208872
* [mips][mips64r6] Add addiupc, aluipc, and auipcDaniel Sanders2014-05-152-2/+8
| | | | | | | | | | | | | | | | Summary: No support for symbols in place of the immediate yet since it requires new relocations. Depends on D3671 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3689 llvm-svn: 208858
* [mips][mips64r6] Add aui, daui, dahi, and datiDaniel Sanders2014-05-152-0/+5
| | | | | | | | | | | | Summary: Depends on D3671 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3759 llvm-svn: 208857
* [mips][mips64r6] Test that branch likelies are not accepted on MIPS64r6.Daniel Sanders2014-05-152-0/+36
| | | | | | | | | | | | | | | Summary: They aren't implemented for any ISA at the moment. Depends on D3670 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3671 llvm-svn: 208855
* [mips] Test that IAS for -mcpu=mips5 does not accept MIPS64 insns and ↵Daniel Sanders2014-05-144-19/+97
| | | | | | | | | | | | | | | | | | | | | | | -mcpu=mips(5|64) does not accept MIPS64r2 Summary: To limit the number of tests required, only one 64-bit ISA prior to MIPS64 are tested. rdhwr has been deliberately left without an ISA annotation for now. This is because the assembler and CodeGen disagree on when the instruction is available. Strictly speaking, it is only available in MIPS32r2 and MIPS64r2. However, it is emulated by a kernel trap on earlier ISA's and is necessary for TLS so CodeGen should emit it on older ISA's too. Depends on D3697 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3698 llvm-svn: 208785
* [mips][mips64r6] Add sel.s and sel.dDaniel Sanders2014-05-142-0/+4
| | | | | | | | | | | | | | | Summary: Also use named constants for common opcode fields. Depends on D3669 Reviewers: vmedic, zoran.jovanovic, jkolek Reviewed By: jkolek Differential Revision: http://reviews.llvm.org/D3670 llvm-svn: 208784
* [mips] Marked up instructions added in MIPS32r2 and tested that IAS for ↵Daniel Sanders2014-05-139-21/+90
| | | | | | | | | | | | | | | | | | | | | | | | | | | -mcpu=mips(2|32) does not accept them Summary: This required a new instruction group representing the 32-bit subset of MIPS-3 that was available in MIPS32R2. To limit the number of tests required, only one 32-bit and one 64-bit ISA prior to MIPS32/MIPS64 are tested. rdhwr has been deliberately left without an ISA annotation for now. This is because the assembler and CodeGen disagree on when the instruction is available. Strictly speaking, it is only available in MIPS32r2 and MIPS64r2. However, it is emulated by a kernel trap on earlier ISA's and is necessary for TLS so CodeGen should emit it on older ISA's too. Depends on D3696 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3697 llvm-svn: 208690
* TableGen: use PrintMethods to print more aliasesTim Northover2014-05-122-4/+4
| | | | llvm-svn: 208607
* [mips] Move disassembler test (test_2r_msa64) into correct folder.Matheus Almeida2014-05-121-6/+0
| | | | llvm-svn: 208594
* [mips] Move disassembler test (Mips MSA test_vec) into correct folder.Matheus Almeida2014-05-121-12/+0
| | | | llvm-svn: 208592
* [mips] Move disassembler tests (Mips MSA test_i*, test_mi10) into correct ↵Matheus Almeida2014-05-124-105/+0
| | | | | | folder. llvm-svn: 208590
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