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* [mips][microMIPS] Implement NOP aliasesJozef Kolek2014-11-293-10/+10
| | | | | | | | | This patch implements microMIPS 16-bit (MOVE16 $0, $0) and 32-bit (SLL $0, $0, 0) NOP aliases. http://reviews.llvm.org/D6440 llvm-svn: 222953
* [mips][microMIPS] Implement SWM16 and LWM16 instructionsZoran Jovanovic2014-11-272-0/+15
| | | | | | Differential Revision: http://reviews.llvm.org/D5579 llvm-svn: 222901
* [mips][microMIPS] Implement BREAK16 and SDBBP16 instructionsJozef Kolek2014-11-271-0/+6
| | | | | | | | Patch by Radovan Obradovic. Differential Revision: http://reviews.llvm.org/D5048 llvm-svn: 222900
* [mips] Add synci instruction.Daniel Sanders2014-11-273-2/+1
| | | | | | | | | | | | | | Patch by Amaury Pouly Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D6421 llvm-svn: 222899
* [mips][microMIPS] Implement disassembler support for 16-bit instructions ↵Jozef Kolek2014-11-261-0/+3
| | | | | | | | LBU16, LHU16, LW16, SB16, SH16 and SW16 Differential Revision: http://reviews.llvm.org/D6405 llvm-svn: 222847
* [mips][microMIPS] Fix JRADDIUSP instructionJozef Kolek2014-11-241-4/+2
| | | | | | | | | Fix JRADDIUSP instruction, remove delay slot flag because this instruction doesn't have delay slot. Differential Revision: http://reviews.llvm.org/D6365 llvm-svn: 222658
* [mips][microMIPS] Implement LBU16, LHU16, LW16, SB16, SH16 and SW16 instructionsJozef Kolek2014-11-242-0/+45
| | | | | | Differential Revision: http://reviews.llvm.org/D5122 llvm-svn: 222653
* [mips][micromips] Implement SWM32 and LWM32 instructionsZoran Jovanovic2014-11-192-24/+55
| | | | | | Differential Revision: http://reviews.llvm.org/D5519 llvm-svn: 222367
* [mips][microMIPS] Fix opcodes of MFHC1 and MTHC1 instructions.Jozef Kolek2014-11-191-0/+6
| | | | | | Differential Revision: http://reviews.llvm.org/D6169 llvm-svn: 222355
* [mips][microMIPS] Implement LWXS instruction.Jozef Kolek2014-11-191-0/+3
| | | | | | Differential Revision: http://reviews.llvm.org/D5407 llvm-svn: 222348
* [mips][microMIPS] Implement SDBBP and RDHWR instructions.Jozef Kolek2014-11-191-0/+15
| | | | | | Differential Revision: http://reviews.llvm.org/D5240 llvm-svn: 222347
* [mips] Add hardware register name "hwr_ulr" ($29)Vasileios Kalintiris2014-11-111-0/+7
| | | | | | | | | | The canonical name when printing assembly is still $29. The reason is that GAS does not accept "$hwr_ulr" at the moment. This addresses the comments from r221307, which reverted the original commit r221299. llvm-svn: 221685
* Recommit "[mips] Add names and tests for the hardware registers"Vasileios Kalintiris2014-11-115-2/+216
| | | | | | | The original commit r221299 was reverted in r221307. I removed the name "hrw_ulr" ($29) from the original commit because two tests were failing. llvm-svn: 221681
* llvm-objdump: Skip empty sections when dumping contentsDavid Majnemer2014-11-112-13/+2
| | | | | | | Empty sections are just noise when using objdump. This is similar to what binutils does. llvm-svn: 221680
* [mips] Improve error/warning messages and testing for the .cpload assembler ↵Toma Tabacu2014-11-062-17/+38
| | | | | | | | | | | | | | | | | | directive. Summary: Improved warning message when using .cpload inside a reorder section and added an error message for using .cpload with Mips16 enabled. Modified the tests to fit with the changes mentioned above, added a test-case for the N32 ABI in cpload.s and did some reformatting to make the tests easier to read. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D5465 llvm-svn: 221447
* [mips][microMIPS] Implement ANDI16 instructionZoran Jovanovic2014-11-052-0/+5
| | | | llvm-svn: 221367
* [mips][microMIPS] Mark symbols as microMIPS if necessaryZoran Jovanovic2014-11-052-0/+89
| | | | | | Differential Revision: http://reviews.llvm.org/D6039 llvm-svn: 221355
* Reverted revisions 221351, 221352 and 221353.Zoran Jovanovic2014-11-052-5/+0
| | | | llvm-svn: 221354
* [mips][microMIPS] Implement ANDI16 instructionZoran Jovanovic2014-11-052-0/+5
| | | | | | Differential Revision: http://reviews.llvm.org/D5163 llvm-svn: 221351
* Revert "[mips] Add names and tests for the hardware registers"Rafael Espindola2014-11-047-225/+4
| | | | | | | | | | | | | This reverts commit r221299. The tests LLVM :: MC/Disassembler/Mips/mips32.txt LLVM :: MC/Disassembler/Mips/mips32_le.txt were failing. llvm-svn: 221307
* [mips] Add names and tests for the hardware registersVasileios Kalintiris2014-11-047-4/+225
| | | | | | | | | | | | Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D5763 llvm-svn: 221299
* [mips] Improve support for the .set mips16/nomips16 assembler directives.Toma Tabacu2014-11-041-0/+10
| | | | | | | | | | | | | | | | | | | Summary: Appropriately set/clear the FeatureBit for Mips16 when these assembler directives are used and also emit ".set nomips16" (previously, only ".set mips16" was being emitted). These improvements allow for better testing of the .cpload/.cprestore assembler directives (which are not supposed to work when Mips16 is enabled). Test Plan: The test is bare-bones because there are no MC tests for Mips16 instructions (there's only one, which checks that the Mips16 ELF header flag gets set), and that suggests to me that it has not been implemented yet in the IAS. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D5462 llvm-svn: 221277
* [mips][microMIPS] Implement ADDIUR1SP instructionZoran Jovanovic2014-10-232-0/+6
| | | | | | Differential Revision: http://reviews.llvm.org/D5153 llvm-svn: 220477
* ps][microMIPS] Implement ADDIUR2 instructionZoran Jovanovic2014-10-232-0/+8
| | | | | | Differential Revision: http://reviews.llvm.org/D5151 llvm-svn: 220476
* ps][microMIPS] Implement LI16 instructionZoran Jovanovic2014-10-232-0/+8
| | | | | | Differential Revision: http://reviews.llvm.org/D5149 llvm-svn: 220475
* [mips][microMIPS] Implement CodeGen support for SLL16 and SRL16 instructionsZoran Jovanovic2014-10-232-0/+10
| | | | | | Differential Revision: http://reviews.llvm.org/D5774 llvm-svn: 220474
* Fix Mips nacl-mask test for new bundle-aligned label behaviorDerek Schuff2014-10-221-4/+5
| | | | | | | After r220439 the behavior of labels in bundle-align mode changed, and I neglected to update this test. llvm-svn: 220447
* [mips][microMIPS] Implement ADDU16 and SUBU16 instructionsZoran Jovanovic2014-10-212-0/+8
| | | | | | Differential Revision: http://reviews.llvm.org/D5118 llvm-svn: 220276
* [mips][microMIPS] Implement AND16, NOT16, OR16 and XOR16 instructionsZoran Jovanovic2014-10-212-0/+16
| | | | | | Differential Revision: http://reviews.llvm.org/D5117 llvm-svn: 220275
* [mips] Add support for COP1's Branch-On-Cond-Likely instructionsVasileios Kalintiris2014-10-1723-14/+94
| | | | | | | | | | | | Summary: Depends on D5782 Reviewers: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D5802 llvm-svn: 220042
* [mips] Add support for COP0's Branch-On-Cond-Likely instructionsVasileios Kalintiris2014-10-1715-24/+192
| | | | | | | | | | | | Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D5782 llvm-svn: 220036
* [mips] Marked the DI/EI instruction aliases as MIPS32r2Vasileios Kalintiris2014-10-1611-4/+75
| | | | | | | | | | | | Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D5751 llvm-svn: 219927
* [mips][microMIPS] Implement ADDIUSP instructionZoran Jovanovic2014-10-102-0/+4
| | | | | | Differential Revision: http://reviews.llvm.org/D5084 llvm-svn: 219500
* [mips][microMIPS] Implement JR16 instructionZoran Jovanovic2014-10-101-0/+5
| | | | | | Differential Revision: http://reviews.llvm.org/D5062 llvm-svn: 219498
* [mips][microMIPS] Implement ADDIUS5 instructionZoran Jovanovic2014-10-102-0/+7
| | | | | | Differential Revision: http://reviews.llvm.org/D5049 llvm-svn: 219495
* ps][microMIPS] Implement JRC instructionZoran Jovanovic2014-10-101-2/+5
| | | | | | Differential Revision: http://reviews.llvm.org/D5045 llvm-svn: 219494
* [mips][microMIPS] Implement JALRS16 instructionZoran Jovanovic2014-10-101-0/+5
| | | | | | Differential Revision: http://reviews.llvm.org/D5027 llvm-svn: 219493
* [mips] Print warning when using register names not available in N32/64Daniel Sanders2014-10-031-3/+23
| | | | | | | | | | | | | | | | | | | Summary: The register names t4-t7 are not available in the N32 and N64 ABIs. This patch prints a warning, when those names are used in N32/64, along with a fix-it with the correct register names. Patch by Vasileios Kalintiris Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D5272 llvm-svn: 218989
* Support padding unaligned data in .text.Joerg Sonnenberger2014-10-021-0/+4
| | | | llvm-svn: 218870
* [mips] Add assembler support for the .set nodsp directive.Toma Tabacu2014-09-171-0/+12
| | | | | | | | | | | | Summary: This directive is used to tell the assembler to reject DSP-specific instructions. Reviewers: dsanders Reviewed By: dsanders Differential Revision: http://reviews.llvm.org/D5142 llvm-svn: 217946
* [mips] Improve the error messages given by MipsAsmParser.Toma Tabacu2014-09-1618-298/+298
| | | | | | | | | | | | Summary: Changed error messages to be more informative and to resemble other clang/llvm error messages (first letter is lower case, no ending punctuation) and updated corresponding tests. Reviewers: dsanders Reviewed By: dsanders Differential Revision: http://reviews.llvm.org/D5065 llvm-svn: 217873
* [mips] Move 32-bit ADDiu instruction alias from Mips64InstrInfo.td to ↵Toma Tabacu2014-09-1611-0/+11
| | | | | | | | | | MipsInstrInfo.td. Patch by Vasileios Kalintiris. Differential Revision: http://reviews.llvm.org/D5244 llvm-svn: 217868
* [mips] Marked the ADDi instruction aliases as not available in Mips32R6 and ↵Toma Tabacu2014-09-1611-0/+44
| | | | | | | | | | Mips64R6. Patch by Vasileios Kalintiris. Differential Revision: http://reviews.llvm.org/D5242 llvm-svn: 217867
* [mips] Marked the DADDiu instruction aliases as MIPS III.Toma Tabacu2014-09-158-0/+32
| | | | | | | | Patch by Vasileios Kalintiris. Differential Revision: http://reviews.llvm.org/D5239 llvm-svn: 217770
* [mips][microMIPS] Implement JRADDIUSP instructionZoran Jovanovic2014-09-121-0/+5
| | | | | | Differential Revision: http://reviews.llvm.org/D5046 llvm-svn: 217681
* [mips][microMIPS] Implement BGEZALS and BLTZALS instructionsZoran Jovanovic2014-09-121-0/+10
| | | | | | Differential Revision: http://reviews.llvm.org/D5004 llvm-svn: 217678
* [mips][microMIPS] Implement JALS and JALRS instructions.Zoran Jovanovic2014-09-121-0/+10
| | | | | | Differential Revision: http://reviews.llvm.org/D5003 llvm-svn: 217676
* [mips][microMIPS] Implement TLBP, TLBR, TLBWI and TLBWR instructionsZoran Jovanovic2014-09-121-0/+12
| | | | | | Differential Revision: http://reviews.llvm.org/D5211 llvm-svn: 217675
* [MIPS] Add aliases for sync instruction used by Octeon CPUKai Nacke2014-09-101-0/+8
| | | | | | | | | This commit adds aliases for the sync instruction (synciobdma, syncs, syncw, syncws) which are used by the Octeon CPU. Reviewed by D. Sanders llvm-svn: 217477
* [mips] Add assembler support for .set mips0 directive.Toma Tabacu2014-09-091-0/+27
| | | | | | | | | | | | | | | | | | Summary: This directive is used to reset the assembler options to their initial values. Assembly programmers use it in conjunction with the ".set mipsX" directives. This patch depends on the .set push/pop directive (http://reviews.llvm.org/D4821). Contains work done by Matheus Almeida. Reviewers: dsanders Reviewed By: dsanders Differential Revision: http://reviews.llvm.org/D4957 llvm-svn: 217438
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