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* [mips] [IAS] Slightly improve shift instruction generation in expandLoadImm.Toma Tabacu2015-05-011-207/+178
| | | | | | | | | | | | | | | | | | | Summary: Generate one DSLL32 of 0 instead of two consecutive DSLL of 16. In order to do this I had to change createLShiftOri's template argument from a bool to an unsigned. This also gave me the opportunity to rewrite the mips64-expansions.s test, as it was testing the same cases multiple times and skipping over other cases. It was also somewhat unreadable, as the CHECK lines were grouped in a huge block of text at the beginning of the file. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8974 llvm-svn: 236311
* [mips][mips64r6] Sorted instructions in test. NFC.Daniel Sanders2015-04-301-96/+96
| | | | llvm-svn: 236221
* [mips][microMIPSr6] Implement MUL, MUH, MULU and MUHU instructionsZoran Jovanovic2015-04-291-0/+4
| | | | | | Differential Revision: http://reviews.llvm.org/D8894 llvm-svn: 236131
* [mips][microMIPSr6] Implement SUB and SUBU instructionsZoran Jovanovic2015-04-291-0/+3
| | | | | | Differential Revision: http://reviews.llvm.org/D8764 llvm-svn: 236118
* [mips][microMIPSr6] Implement ADD, ADDU and ADDIU instructionsZoran Jovanovic2015-04-291-0/+3
| | | | | | Differential Revision: http://reviews.llvm.org/D8704 llvm-svn: 236111
* [mips] [IAS] Do not generate redundant ORi in createLShiftOri.Toma Tabacu2015-04-282-13/+16
| | | | | | | | | | | | | | Summary: If the immediate is 0, the ORi is pointless. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8969 llvm-svn: 235990
* Use CIE version 1 for .eh_frame.Rafael Espindola2015-04-271-4/+4
| | | | | | | | | | According to http://www.linuxbase.org/betaspecs/lsb/LSB-Core-generic/LSB-Core-generic/ehframechpt.html we should always use 1. llvm-svn: 235923
* [mips] [IAS] Improve warning for using AT with .set noat.Toma Tabacu2015-04-271-11/+12
| | | | | | | | | | | | | | | | | Summary: Changed the warning message to show the current value of $at, similar to what clang does for typedef's, and renamed warnIfAssemblerTemporary to a more descriptive name. I also changed the type of variables which store registers from int to unsigned, updated the relevant test and tried to make the related comments clearer. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8479 llvm-svn: 235881
* [mips] [IAS] Implement the .asciiz directive.Toma Tabacu2015-04-212-0/+36
| | | | | | | | | | | | | | | | Summary: This directive is exactly the same as .asciz, except it's only used by MIPS. It is used to store null terminated strings in object files. Reviewers: rafael, dsanders, echristo Reviewed By: dsanders, echristo Subscribers: echristo, llvm-commits Differential Revision: http://reviews.llvm.org/D7530 llvm-svn: 235382
* [mips][microMIPSr6] Implement CACHE and PREF instructionsJozef Kolek2015-04-211-0/+2
| | | | | | | | Implement CACHE and PREF instructions using mapping. Differential Revision: http://reviews.llvm.org/D8893 llvm-svn: 235379
* [mips][microMIPSr6] Implement BITSWAP instructionJozef Kolek2015-04-201-0/+1
| | | | | | | | Implement BITSWAP instruction using mapping. Differential Revision: http://reviews.llvm.org/D8857 llvm-svn: 235321
* [mips][microMIPSr6] Implement BALC and BC instructionsJozef Kolek2015-04-201-0/+5
| | | | | | | | This patch implements BALC and BC instructions using mapping. Differential Revision: http://reviews.llvm.org/D8388 llvm-svn: 235302
* [mips] [IAS] Preserve microMIPS label marking for objects when assigning.Toma Tabacu2015-04-161-0/+12
| | | | | | | | | | | | | | Summary: Previously, this was only happening for functions, but because of .insn, objects can also be marked now. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8007 llvm-svn: 235095
* [mips] [IAS] Add support for the .insn directive.Toma Tabacu2015-04-161-0/+98
| | | | | | | | | | | | | | | | | Summary: This assembler directive marks the current label as an instruction label in microMIPS and MIPS16. This initial implementation works only for microMIPS. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8006 llvm-svn: 235084
* Update tests to not be as dependent on section numbers.Rafael Espindola2015-04-151-1/+1
| | | | | | | | Many of these predate llvm-readobj. With elf-dump we had to match a relocation to symbol number and symbol number to symbol name or section number. llvm-svn: 235015
* Re-enable target-specific relocation table sorting and use it for MipsPetar Jovanovic2015-04-142-1/+126
| | | | | | | | | | | | | | Some targets (ie. Mips) have additional rules for ordering the relocation table entries. Allow them to override generic sortRelocs(), which sorts entries by Offset. Then override this function for Mips, to emit HI16 and GOT16 relocations against the local symbol in pair with the corresponding LO16 relocation. Patch by Vladimir Stefanovic. Differential Revision: http://reviews.llvm.org/D7414 llvm-svn: 234883
* [mips] [IAS] Make the mips-expansions-bad.s test more readable. NFC.Toma Tabacu2015-04-101-3/+5
| | | | | | | Move the check lines below the code lines and change the indentation from 8 spaces to 2 spaces. llvm-svn: 234584
* [mips] [IAS] Do not generate redundant move when expanding lw/sw with symbol.Toma Tabacu2015-04-081-0/+14
| | | | | | | | | | | | | | | | | | Summary: Even though there is no 2nd register operand in the "lw/sw $8, symbol" case, we still try to find one, and we end up with $0, which makes us generate an unnecessary "addu $8, $8, $0" (a.k.a. "move $8, $8"). We can avoid this by checking if the 2nd register operand is different from $0, before generating the addu. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8055 llvm-svn: 234406
* [mips] [IAS] Add support for the BNEZL and BEQZL pseudo-instructions.Toma Tabacu2015-04-081-0/+6
| | | | | | | | | | | | | | | | | Summary: They are of the form "bnezl/beqzl $rs, offset" and expand to "bnel/beql $rs, $zero, offset". These instructions are used in Linux inline assembly. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8540 llvm-svn: 234401
* [mips] [IAS] Remove AssemblerPredicate's from RelocPIC and RelocStatic.Toma Tabacu2015-04-0815-15/+120
| | | | | | | | | | | | | | | | Summary: These AssemblerPredicate's are unnecessary and actually make some instructions unusable when assembling pre-MIPS32 ISAs. For example, this was causing the IAS to reject the 'j' instruction for MIPS I-V. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8300 llvm-svn: 234398
* [mips] [IAS] Allow .set assignments for already defined symbols.Toma Tabacu2015-04-071-0/+18
| | | | | | | | | | | | | | | | Summary: This is not possible when using the IAS for MIPS, but it is possible when using the IAS for other architectures and when using GAS for MIPS. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8578 llvm-svn: 234316
* [mips] [IAS] Add support for the XOR $reg,imm pseudo-instruction.Toma Tabacu2015-03-1715-0/+15
| | | | | | | | | | | | | | | | Summary: This adds a MipsInstAlias which expands to XORi $reg,$reg,imm. For example, "xor $6, 0x3A" should be expanded to "xori $6, $6, 58". This should work for all MIPS ISAs. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8284 llvm-svn: 232473
* [opaque pointer type] Add textual IR support for explicit type parameter to ↵David Blaikie2015-03-132-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | gep operator Similar to gep (r230786) and load (r230794) changes. Similar migration script can be used to update test cases, which successfully migrated all of LLVM and Polly, but about 4 test cases needed manually changes in Clang. (this script will read the contents of stdin and massage it into stdout - wrap it in the 'apply.sh' script shown in previous commits + xargs to apply it over a large set of test cases) import fileinput import sys import re rep = re.compile(r"(getelementptr(?:\s+inbounds)?\s*\()((<\d*\s+x\s+)?([^@]*?)(|\s*addrspace\(\d+\))\s*\*(?(3)>)\s*)(?=$|%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|zeroinitializer|<|\[\[[a-zA-Z]|\{\{)", re.MULTILINE | re.DOTALL) def conv(match): line = match.group(1) line += match.group(4) line += ", " line += match.group(2) return line line = sys.stdin.read() off = 0 for match in re.finditer(rep, line): sys.stdout.write(line[off:match.start()]) sys.stdout.write(conv(match)) off = match.end() sys.stdout.write(line[off:]) llvm-svn: 232184
* [mips] [IAS] Add missing constraints and improve testing for the .module ↵Toma Tabacu2015-03-062-6/+262
| | | | | | | | | | | | | | | | | | directive. Summary: None of the .set directives can be used before the .module directives. The .set mips0/pop/push were not triggering this constraint. Also added testing for all the other implemented directives which are supposed to trigger this constraint. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D7140 llvm-svn: 231465
* [opaque pointer type] Add textual IR support for explicit type parameter to ↵David Blaikie2015-02-271-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
* Replace obsolete -mattr=n64 command line option with -target-abi=n64. No ↵Vladimir Medic2015-02-262-2/+2
| | | | | | functional changes. llvm-svn: 230628
* [MIPS]Multiple and add instructions for Mips are currently available in ↵Vladimir Medic2015-02-2512-48/+24
| | | | | | mips32r2/mips64r2 and later but should also be available in mips4, mips5, and mips64. This patch fixes the requested features and updates the corresponding test files. llvm-svn: 230500
* [mips][microMIPS] Implement JALX instructionJozef Kolek2015-02-181-0/+5
| | | | | | Differential Revision: http://reviews.llvm.org/D5047 llvm-svn: 229702
* [mips] Add backend support for Mips32r[35] and Mips64r[35].Daniel Sanders2015-02-1824-0/+2590
| | | | | | | | | | | | | | | | | Summary: These ISA's didn't add any instructions so they are almost identical to Mips32r2 and Mips64r2. Even the ELF e_flags are the same, However the ISA revision in .MIPS.abiflags is 3 or 5 respectively instead of 2. Reviewers: vmedic Reviewed By: vmedic Subscribers: tomatabacu, llvm-commits, atanasyan Differential Revision: http://reviews.llvm.org/D7381 llvm-svn: 229695
* [mips] [IAS] Fix using .cpsetup with local labels (PR22518).Toma Tabacu2015-02-182-2/+43
| | | | | | | | | | | | | | | | | Summary: Parse for an MCExpr instead of an Identifier and use the symbol for relocations, not just the symbol's name. This fixes errors when using local labels in .cpsetup (PR22518). Reviewers: dsanders Reviewed By: dsanders Subscribers: seanbruno, emaste, llvm-commits Differential Revision: http://reviews.llvm.org/D7697 llvm-svn: 229671
* [mips] Improve support for the .set at/noat assembler directives.Toma Tabacu2015-02-134-0/+74
| | | | | | | | | | | | | | | | | | | | | Summary: Made the following changes: Added calls to emitDirectiveSetNoAt() and emitDirectiveSetAt(). Added special emit function for .set at=$reg, emitDirectiveSetAtWithArg(unsigned RegNo). Improved parsing error checks for .set at. Refactored parser code for .set at. Improved testing of both directives. Improved code readability and comments. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D7176 llvm-svn: 229097
* [mips][microMIPS] Implement movep instructionZoran Jovanovic2015-02-102-0/+7
| | | | | | Differential Revision: http://reviews.llvm.org/D7465 llvm-svn: 228703
* [mips] Fix FileCheck prefixes with whitespace between 'CHECK' and ':'Daniel Sanders2015-02-061-8/+4
| | | | llvm-svn: 228403
* [mips] Manually replace JAL pseudo-instructions with their JALR equivalent, ↵Toma Tabacu2015-01-301-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | instead of using InstAlias. Summary: This is needed by the .cprestore assembler directive. This directive needs to be able to insert an LW instruction after every JALR replacement of a JAL pseudo-instruction (and never after a JALR which has NOT been a result of a pseudo-instruction replacement). The problem with using InstAlias for these is that after it replaces the pseudo-instruction, we can't find out if the resulting JALR instruction was generated by an InstAlias or not, so we don't know whether or not to insert our LW instruction. By replacing it manually, we know when the pseudo-instruction replacement happens and we can insert the LW instruction correctly. Reviewers: dsanders Reviewed By: dsanders Subscribers: emaste, llvm-commits Differential Revision: http://reviews.llvm.org/D5601 llvm-svn: 227568
* [mips][microMIPS] Implement SWM and LWM aliasesZoran Jovanovic2015-01-281-0/+24
| | | | | | Differential Revision: http://reviews.llvm.org/D5820 llvm-svn: 227373
* [mips][microMIPS] Implement LWGP instructionJozef Kolek2015-01-282-0/+6
| | | | | | Differential Revision: http://reviews.llvm.org/D6650 llvm-svn: 227325
* [mips] Add range checks and transformation to octeon instructions in AsmParser.Kai Nacke2015-01-271-0/+12
| | | | | | | | | | | | | | | | | This patch adds range checks to the immediate operands of octeon instructions in the AsmParser. Like gas, it applies the following transformations if the immediate is to large: bbit0 $8, 42, foo => bbit032 $8, 10, foo bbit1 $8, 46, foo => bbit132 $8, 14, foo cins $8, $31, 32, 31 => cins32 $8, $31, 0, 31 exts $7, $4, 54, 9 => exts32 $7, $4, 22, 9 Reviewed By: dsanders Differential Revision: http://reviews.llvm.org/D7080 llvm-svn: 227225
* Move the Mips target to storing the ABI in the TargetMachine ratherEric Christopher2015-01-2611-31/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | | than on MipsSubtargetInfo. This required a bit of massaging in the MC level to handle this since MC is a) largely a collection of disparate classes with no hierarchy, and b) there's no overarching equivalent to the TargetMachine, instead only the subtarget via MCSubtargetInfo (which is the base class of TargetSubtargetInfo). We're now storing the ABI in both the TargetMachine level and in the MC level because the AsmParser and the TargetStreamer both need to know what ABI we have to parse assembly and emit objects. The target streamer has a pointer to the one in the asm parser and is updated when the asm parser is created. This is fragile as the FIXME comment notes, but shouldn't be a problem in practice since we always create an asm parser before attempting to emit object code via the assembler. The TargetMachine now contains the ABI so that the DataLayout can be constructed dependent upon ABI. All testcases have been updated to use the -target-abi command line flag so that we can set the ABI without using a subtarget feature. Should be no change visible externally here. llvm-svn: 227102
* [mips] Add new error message and improve testing for parsing the .module ↵Toma Tabacu2015-01-231-13/+23
| | | | | | | | | | | | | | | | | | | | | | | directive. Summary: We used to silently ignore any empty .module's and we used to give an error saying that we found an "unexpected token at start of statement" when the value of the option wasn't an identifier (e.g. if it was a number). We now give an error saying that we "expected .module option identifier" in both of those cases. I also fixed the other tests in mips-abi-bad.s, which all seemed to be broken. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D7095 llvm-svn: 226905
* [mips][microMIPS] MicroMIPS 16-bit unconditional branch instruction BJozef Kolek2015-01-215-34/+43
| | | | | | | | | | | | | | Implement microMIPS 16-bit unconditional branch instruction B. Implemented 16-bit microMIPS unconditional instruction has real name B16, and B is an alias which expands to either B16 or BEQ according to the rules: b 256 --> b16 256 # R_MICROMIPS_PC10_S1 b 12256 --> beq $zero, $zero, 12256 # R_MICROMIPS_PC16_S1 b label --> beq $zero, $zero, label # R_MICROMIPS_PC16_S1 Differential Revision: http://reviews.llvm.org/D3514 llvm-svn: 226657
* [mips][microMIPS] Implement ADDIUPC instructionJozef Kolek2015-01-212-0/+12
| | | | | | Differential Revision: http://reviews.llvm.org/D6582 llvm-svn: 226656
* Reverted revision 226577.Jozef Kolek2015-01-204-110/+5
| | | | llvm-svn: 226595
* [mips][microMIPS] MicroMIPS 16-bit unconditional branch instruction BJozef Kolek2015-01-204-5/+110
| | | | | | | | | | | | | | Implement microMIPS 16-bit unconditional branch instruction B. Implemented 16-bit microMIPS unconditional instruction has real name B16, and B is an alias which expands to either B16 or BEQ according to the rules: b 256 --> b16 256 # R_MICROMIPS_PC10_S1 b 12256 --> beq $zero, $zero, 12256 # R_MICROMIPS_PC16_S1 b label --> beq $zero, $zero, label # R_MICROMIPS_PC16_S1 Differential Revision: http://reviews.llvm.org/D3514 llvm-svn: 226577
* [mips] Add octeon branch instructions bbit0/bbit032/bbit1/bbit132Kai Nacke2015-01-201-0/+9
| | | | | | | | | This commits adds the octeon branch instructions bbit0/bbit032/bbit1/bbit132. It also includes patterns for instruction selection and test cases. Reviewed by D. Sanders llvm-svn: 226573
* [mips][microMIPS] Implement BEQZ16 and BNEZ16 instructionsJozef Kolek2015-01-124-0/+47
| | | | | | Differential Revision: http://reviews.llvm.org/D5271 llvm-svn: 225627
* [mips][microMIPS] Relocate with symbol for micromips symbolsZoran Jovanovic2014-12-301-0/+16
| | | | | | Differential Revision: http://reviews.llvm.org/D6796 llvm-svn: 225008
* [mips][microMIPS] Implement CACHE, PREF, SSNOP, EHB and PAUSE instructionsJozef Kolek2014-12-232-0/+17
| | | | | | Differential Revision: http://reviews.llvm.org/D5204 llvm-svn: 224785
* [mips][microMIPS] Implement LWSP and SWSP instructionsJozef Kolek2014-12-232-0/+12
| | | | | | Differential Revision: http://reviews.llvm.org/D6416 llvm-svn: 224771
* [mips][microMIPS] Implement SWP and LWP instructionsZoran Jovanovic2014-12-161-0/+6
| | | | | | Differential Revision: http://reviews.llvm.org/D5667 llvm-svn: 224338
* The andi16, addiusp and jraddiusp micromips instructions were missing ↵Vladimir Medic2014-12-011-0/+12
| | | | | | dedicated decoder methods in MipsDisassembler.cpp to properly decode immediate operands. These methods are added together with corresponding tests. llvm-svn: 223006
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