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* Bring r240130 back.Rafael Espindola2015-06-223-9/+9
| | | | | | | | | | | | | | | | | | | | | | Now that pr23900 is fixed, we can bring it back with no changes. Original message: Make all temporary symbols unnamed. What this does is make all symbols that would otherwise start with a .L (or L on MachO) unnamed. Some of these symbols still show up in the symbol table, but we can just make them unnamed. In order to make sure we produce identical results when going thought assembly, all .L (not just the compiler produced ones), are now unnamed. Running llc on llvm-as.opt.bc, the peak memory usage goes from 208.24MB to 205.57MB. llvm-svn: 240302
* [mips] [IAS] Add support for LAReg with identical source and destination ↵Toma Tabacu2015-06-221-0/+6
| | | | | | | | | | | | | | | | register operands. Summary: In this case, we're supposed to load the immediate in AT and then ADDu it with the source register and put it in the destination register. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D9367 llvm-svn: 240278
* [mips] [IAS] Add support for LASym with identical source and destination ↵Toma Tabacu2015-06-221-0/+6
| | | | | | | | | | | | | | | | | | register operands. Summary: In this case, we're supposed to load the address of the symbol in AT and then ADDu it with the source register and put it in the destination register. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D9366 llvm-svn: 240273
* Revert 240130, it caused crashes (repro in PR23900).Nico Weber2015-06-193-9/+9
| | | | llvm-svn: 240193
* Make all temporary symbols unnamed.Rafael Espindola2015-06-193-9/+9
| | | | | | | | | | | | | | | | What this does is make all symbols that would otherwise start with a .L (or L on MachO) unnamed. Some of these symbols still show up in the symbol table, but we can just make them unnamed. In order to make sure we produce identical results when going thought assembly, all .L (not just the compiler produced ones), are now unnamed. Running llc on llvm-as.opt.bc, the peak memory usage goes from 208.24MB to 205.57MB. llvm-svn: 240130
* [MC/Dwarf] Encode DW_CFA_advance_loc in target endianess.Benjamin Kramer2015-06-171-0/+68
| | | | | | This matches GNU as output. llvm-svn: 239911
* [mips] [IAS] Add support for expanding LASym with a source register operand.Toma Tabacu2015-06-171-0/+6
| | | | | | | | | | | | Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D9348 llvm-svn: 239910
* [mips] [IAS] Add support for the B{L,G}{T,E}(U) branch pseudo-instructions.Toma Tabacu2015-06-173-0/+322
| | | | | | | | | | | | | | | | Summary: This does not include support for the immediate variants of these pseudo-instructions. Fixes llvm.org/PR20968. Reviewers: dsanders Reviewed By: dsanders Subscribers: seanbruno, emaste, llvm-commits Differential Revision: http://reviews.llvm.org/D8537 llvm-svn: 239905
* [mips] [IAS] Fix LA with relative label operands.Toma Tabacu2015-06-171-0/+5
| | | | | | | | | | | | | | | | | Summary: Call MCSymbolRefExpr::create() with a MCSymbol* argument, not with a StringRef of the Symbol's name, in order to avoid creating invalid temporary symbols for relative labels (e.g. {$,.L}tmp00, {$,.L}tmp10 etc.). Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D10498 llvm-svn: 239901
* [mips] [IAS] Add test for SW with relative label operands. NFC.Toma Tabacu2015-06-171-0/+5
| | | | | | | | | | | | Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D10497 llvm-svn: 239899
* [mips] [IAS] Fix LW with relative label operands.Toma Tabacu2015-06-171-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Previously, MCSymbolRefExpr::create() was called with a StringRef of the symbol name, which it would then search for in the Symbols StringMap (from MCContext). However, relative labels (which are temporary symbols) are apparently not stored in the Symbols StringMap, so we end up creating a new {$,.L}tmp symbol ({$,.L}tmp00, {$,.L}tmp10 etc.) each time we create an MCSymbolRefExpr by passing in the symbol name as a StringRef. Fortunately, there is a version of MCSymbolRefExpr::create() which takes an MCSymbol* and we already have an MCSymbol* at that point, so we can just pass that in instead of the StringRef. I also removed the local StringRef calls to MCSymbolRefExpr::create() from expandMemInst(), as those cases can be handled by evaluateRelocExpr() anyway. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D9938 llvm-svn: 239897
* [mips][ias] Expand on r238751 to cover as many relocs as possible.Daniel Sanders2015-06-162-45/+204
| | | | | | | | | | | | | | | | | | | | | | | Summary: Relocs that can be converted from absolute to PC-relative now do so if IsPCRel is true. Relocs that require PC-relative now call llvm_unreachable() if IsPCRel is false and similarly those that require absolute assert that IsPCRel is false. Note that while it looks like some relocs (e.g. R_MIPS_26) can be converted into the MIPS32r6/MIPS64r6 relocs (R_MIPS_PC*_S2), it isn't actually valid to do so. Placeholders have been left in the testcase for unsupported relocs and relocs that cannot be generated at the moment. Reviewers: vkalintiris Reviewed By: vkalintiris Subscribers: llvm-commits, rafael Differential Revision: http://reviews.llvm.org/D10184 llvm-svn: 239817
* Recommit "[mips] [IAS] Add support for BNE and BEQ with an immediate ↵Toma Tabacu2015-06-114-0/+158
| | | | | | | | | operand." (r239396). Apparently, Arcanist didn't include some of my local changes in my previous commit attempt. llvm-svn: 239523
* [mips][microMIPS] Implement ERET and ERETNC instructionsZoran Jovanovic2015-06-111-0/+2
| | | | | | http://reviews.llvm.org/D10091 llvm-svn: 239522
* [mips] Change existing uimm10 operand to restrict the accepted immediatesZoran Jovanovic2015-06-113-0/+13
| | | | | | http://reviews.llvm.org/D10312 llvm-svn: 239520
* Recommit "[mips] [IAS] Restore STI.FeatureBits in .set pop." (r239144).Toma Tabacu2015-06-092-0/+26
| | | | | | | Specified the llvm namespace for the 2 calls to make_unique() which caused compilation errors in Visual Studio 2013. llvm-svn: 239405
* Revert "[mips] [IAS] Add support for BNE and BEQ with an immediate operand." ↵Toma Tabacu2015-06-094-158/+0
| | | | | | | | (r239396). It was breaking buildbots. llvm-svn: 239397
* [mips] [IAS] Add support for BNE and BEQ with an immediate operand.Toma Tabacu2015-06-094-0/+158
| | | | | | | | | | | | | | | | Summary: For some branches, GAS accepts an immediate instead of the 2nd register operand. We only implement this for BNE and BEQ for now. Other branch instructions can be added later, if needed. Reviewers: dsanders Reviewed By: dsanders Subscribers: seanbruno, emaste, llvm-commits Differential Revision: http://reviews.llvm.org/D9666 llvm-svn: 239396
* Revert "[mips] [IAS] Restore STI.FeatureBits in .set pop." (r239144).Toma Tabacu2015-06-052-26/+0
| | | | | | This is breaking the Windows buildbots. llvm-svn: 239145
* [mips] [IAS] Restore STI.FeatureBits in .set pop.Toma Tabacu2015-06-052-0/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Only restoring AvailableFeatures is not enough and will lead to buggy behaviour. For example, if we have a feature enabled and we ".set pop", the next time we try to ".set" that feature nothing will happen because the "!(STI.getFeatureBits()[Feature])" check will be false, because we didn't restore STI.FeatureBits. In order to fix this, we need to make MipsAssemblerOptions remember the STI.FeatureBits instead of the AvailableFeatures and then regenerate AvailableFeatures each time we ".set pop". This is because, AFAIK, there is no way to convert from AvailableFeatures back to STI.FeatureBits, but the reverse is possible by using ComputeAvailableFeatures(STI.FeatureBits). I also moved the updating of AssemblerOptions inside the "if" statement in setFeatureBits() and clearFeatureBits(), as there is no reason to update if nothing changes. Reviewers: dsanders, mkuper Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D9156 llvm-svn: 239144
* llvm-readobj can parse relocations, no need to check the raw bytes.xRafael Espindola2015-06-041-11/+7
| | | | llvm-svn: 239041
* [mips] [IAS] Reformat mips-expansions.s. NFC.Toma Tabacu2015-06-021-33/+32
| | | | | | | | | | | | | | | | | | Summary: Make mips-expansions.s more readable by grouping the instructions with their respective CHECK's. This test is going to get a lot bigger soon and it will become essentially unreadable if the current formatting is kept. I've also made the comments more useful and accurate, and I've restricted the RUN lines to under 80 columns. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D10089 llvm-svn: 238817
* [mips] Test both %dtprel_hi and %dtprel_lo instead of testing %dtprel_hi twice.Daniel Sanders2015-06-021-3/+3
| | | | | | The second %dtprel_hi is used on an addiu so it looks like a copy/paste error. llvm-svn: 238815
* [mips] Expand tabs in test/MC/Mips/mips-relocations.sDaniel Sanders2015-06-021-11/+11
| | | | llvm-svn: 238814
* [mips] [IAS] Add support for the .set softfloat/hardfloat directives.Toma Tabacu2015-06-022-0/+26
| | | | | | | | | | | | | | Summary: These directives are used to set the current value of the SoftFloat feature. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits, mpf Differential Revision: http://reviews.llvm.org/D9074 llvm-svn: 238813
* Fix relocation selection for foo-. on mips.Rafael Espindola2015-06-011-0/+10
| | | | | | This handles only the 32 bit case. llvm-svn: 238751
* [mips] Add new format for dmtc2/dmfc2 for Octeon CPUs.Kai Nacke2015-05-281-0/+4
| | | | | | | | | | | | | Octeon CPUs use dmtc2 rt,imm16 and dmfcp2 rt,imm16 for the crypto coprocessor. E.g. dmtc2 rt,0x4057 starts calculation of sha-1. I had to introduce a new deconding namespace to avoid a decoding conflict. Reviewed By: dsanders Differential Revision: http://reviews.llvm.org/D10083 llvm-svn: 238439
* [mips][microMIPSr6] Implement SEB and SEH instructionsZoran Jovanovic2015-05-271-0/+2
| | | | | | Differential Revision: http://reviews.llvm.org/D9739 llvm-svn: 238333
* [mips][microMIPSr6] Implement BEQZALC, BGEZALC, BGTZALC, BLEZALC, BLTZALC ↵Jozef Kolek2015-05-271-0/+6
| | | | | | | | | | | and BNEZALC instructions This patch implements microMIPS32r6 BEQZALC, BGEZALC, BGTZALC, BLEZALC, BLTZALC and BNEZALC instructions using mapping. Differential Revision: http://reviews.llvm.org/D10031 llvm-svn: 238325
* Relax these tests a bit.Rafael Espindola2015-05-221-2/+2
| | | | | | It is not relevant where in the string table the name is located. llvm-svn: 238053
* [mips] [IAS] Add 2 missing CHECK directives for fixups in mips-expansions.s.Toma Tabacu2015-05-211-2/+2
| | | | llvm-svn: 237884
* [mips][microMIPSr6] Implement NOR, OR, ORI, XOR and XORI instructionsZoran Jovanovic2015-05-191-0/+5
| | | | | | Differential Revision: http://reviews.llvm.org/D8800 llvm-svn: 237697
* [mips][microMIPSr6] Implement AND and ANDI instructionsZoran Jovanovic2015-05-191-0/+2
| | | | | | Differential Revision: http://reviews.llvm.org/D8772 llvm-svn: 237696
* [mips][microMIPSr6] Implement DIV, DIVU, MOD and MODU instructionsZoran Jovanovic2015-05-191-0/+4
| | | | | | Differential Revision: http://reviews.llvm.org/D8769 llvm-svn: 237685
* [mips][microMIPSr6] Implement LSA instructionJozef Kolek2015-05-181-0/+1
| | | | | | | | This patch implements LSA instruction using mapping. Differential Revision: http://reviews.llvm.org/D8919 llvm-svn: 237634
* [mips][microMIPSr6] Implement ALIGN and AUI instructionsJozef Kolek2015-05-181-0/+2
| | | | | | | | This patch implements ALIGN and AUI instructions using mapping. Differential Revision: http://reviews.llvm.org/D8782 llvm-svn: 237563
* [mips] [IAS] Fix expansion of negative 32-bit immediates for LI/DLI.Toma Tabacu2015-05-152-0/+18
| | | | | | | | | | | | | | | | | | Summary: To maintain compatibility with GAS, we need to stop treating negative 32-bit immediates as 64-bit values when expanding LI/DLI. This currently happens because of sign extension. To do this we need to choose the 32-bit value expansion for values which use their upper 33 bits only for sign extension (i.e. no 0's, only 1's). Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8662 llvm-svn: 237428
* [mips] [IAS] Enforce .set nomacro.Toma Tabacu2015-05-142-0/+79
| | | | | | | | | | | | | | Summary: When used, ".set nomacro" causes warning messages to be reported when we expand pseudo-instructions to multiple machine instructions. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D9564 llvm-svn: 237366
* [mips] [IAS] Emit .set macro/nomacro.Toma Tabacu2015-05-142-2/+4
| | | | | | | | | | | | Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D9563 llvm-svn: 237363
* [mips] [IAS] Warn when LA is used with a 64-bit symbol.Toma Tabacu2015-05-142-17/+9
| | | | | | | | | | | | Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D9295 llvm-svn: 237356
* [mips][microMIPSr6] Implement CLO and CLZ instructionsJozef Kolek2015-05-131-0/+2
| | | | | | | | This patch implements CLO and CLZ instructions using mapping. Differential Revision: http://reviews.llvm.org/D8553 llvm-svn: 237257
* [mips] [IAS] Unify common functionality of LA and LI.Toma Tabacu2015-05-133-4/+10
| | | | | | | | | | | | | | Summary: A side-effect of this is that LA gains proper handling of unsigned and positive signed 16-bit immediates and more accurate error messages. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D9290 llvm-svn: 237255
* [mips] [IAS] Merge the micromips-expressions.s test into expr1.s. NFC.Toma Tabacu2015-05-132-49/+32
| | | | | | | | | | | | | | Summary: Also did some minor reformatting in the resulting test. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D9702 llvm-svn: 237242
* [mips][microMIPSr6] Implement SELEQZ and SELNEZ instructionsJozef Kolek2015-05-121-0/+2
| | | | | | | | This patch implements SELEQZ and SELNEZ instructions using mapping. Differential Revision: http://reviews.llvm.org/D8497 llvm-svn: 237158
* [mips][microMIPSr6] Implement ALUIPC and AUIPC instructionsJozef Kolek2015-05-081-0/+2
| | | | | | | | This patch implements ALUIPC and AUIPC instructions using mapping. Differential Revision: http://reviews.llvm.org/D8441 llvm-svn: 236858
* [mips][microMIPSr6] Implement ADDIUPC and LWPC instructionsJozef Kolek2015-05-081-0/+2
| | | | | | | | This patch implements ADDIUPC and LWPC instructions using mapping. Differential Revision: http://reviews.llvm.org/D8415 llvm-svn: 236852
* [mips][microMIPSr6] Implement JIALC and JIC instructionsJozef Kolek2015-05-071-0/+2
| | | | | | | | This patch implements JIALC and JIC instructions using mapping. Differential Revision: http://reviews.llvm.org/D8389 llvm-svn: 236748
* [mips] Add the SoftFloat MipsSubtarget feature.Toma Tabacu2015-05-071-0/+331
| | | | | | | | | | | | | | Summary: This will enable the IAS to reject floating point instructions if soft-float is enabled. Reviewers: dsanders, echristo Reviewed By: dsanders Subscribers: jfb, llvm-commits, mpf Differential Revision: http://reviews.llvm.org/D9053 llvm-svn: 236713
* [mips][msa] Test basic operations for the N32 ABI too.Daniel Sanders2015-05-0511-0/+33
| | | | | | | | | | | | | | | | | Summary: This required adding instruction aliases for dneg. N64 will be enabled shortly but requires additional bugfixes. Reviewers: vkalintiris Reviewed By: vkalintiris Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D9341 llvm-svn: 236489
* [mips] [IAS] Fix error messages for using LI with 64-bit immediates.Toma Tabacu2015-05-011-3/+6
| | | | | | | | | | | | | | | | Summary: LI should never accept immediates larger than 32 bits. The additional Is32BitImm boolean also paves the way for unifying the functionality that LA and LI have in common. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D9289 llvm-svn: 236313
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