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* [mips][ias] Implement ulh macro.Daniel Sanders2015-10-153-2/+217
| | | | | | | | | | | | | | Summary: This macro is needed to prevent test/CodeGen/Mips/2008-08-01-AsmInline.ll from failing after the integrated assembler is enabled by default. Reviewers: vkalintiris Subscribers: llvm-commits, dsanders Differential Revision: http://reviews.llvm.org/D13654 llvm-svn: 250414
* [mips][microMIPS] Implement DPA.W.PH, DPAQ_S.W.PH, DPAQ_SA.L.W, ↵Zlatko Buljan2015-10-151-1/+4
| | | | | | | | DPAQX_S.W.PH, DPAQX_SA.W.PH, DPAU.H.QBL, DPAU.H.QBR and DPAX.W.PH instructions Differential Revision: http://reviews.llvm.org/D13376 llvm-svn: 250382
* [mips][microMIPS] Implement BREAK16, LI16, MOVE16, SDBBP16, SUBU16 and XOR16 ↵Hrvoje Varga2015-10-152-0/+12
| | | | | | | | instructions Differential Revision: http://reviews.llvm.org/D11292#inline-103143 llvm-svn: 250381
* [mips][microMIPS] Implement LLE and SCE instructionsHrvoje Varga2015-10-151-0/+6
| | | | | | Differential Revision: http://reviews.llvm.org/D11630 llvm-svn: 250379
* [mips][microMIPS] Implement LWLE, LWRE, SWLE and SWRE instructionsHrvoje Varga2015-10-152-0/+13
| | | | | | Differential Revision: http://reviews.llvm.org/D11631 llvm-svn: 250377
* [mips][micromips] Initial support for micrmomips DSP instructions and ↵Zoran Jovanovic2015-10-121-0/+5
| | | | | | | | addu.qb implementation Differential Revision: http://reviews.llvm.org/D12798 llvm-svn: 250058
* [mips][ias] Implement macro expansion when bcc has an immediate where a ↵Daniel Sanders2015-10-122-0/+81
| | | | | | | | | | | | | | register belongs. Summary: Fixes PR24915. Reviewers: vkalintiris Subscribers: emaste, seanbruno, llvm-commits Differential Revision: http://reviews.llvm.org/D13533 llvm-svn: 250042
* [mips][microMIPS] Implement JALRC16, JRCADDIUSP and JRC16 instructionsZoran Jovanovic2015-10-055-0/+33
| | | | | | Differential Revision: http://reviews.llvm.org/D11219 llvm-svn: 249317
* [mips] Changed the way symbols are handled in dla and la instructions to ↵Daniel Sanders2015-10-053-38/+75
| | | | | | | | | | | | | | | | | | | | | allow simple expressions. Summary: An instruction like "(d)la $5, symbol+8" previously would have crashed the assembler as it contains an expression. This is now fixed. A few tests cases have also been changed to reflect these changes, however these should only be syntax changes. Some new test cases have also been added. Patch by Scott Egerton. Reviewers: vkalintiris, dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D12760 llvm-svn: 249311
* [mips][microMIPS] Implement CACHEE, WRPGPR and WSBH instructionsZoran Jovanovic2015-10-014-0/+13
| | | | | | Differential Revision: http://reviews.llvm.org/D10337 llvm-svn: 249004
* [mips] Handling of immediates bigger than 16 bitsZoran Jovanovic2015-09-281-0/+273
| | | | | | Differential Revision: http://reviews.llvm.org/D10539 llvm-svn: 248706
* Use ELFOSABI_NONE instead of ELFOSABI_LINUX.Rafael Espindola2015-09-241-1/+1
| | | | | | | | | | | | The doesn't seem to be a difference and ELFOSABI_NONE seems to be far more common: * Linux doesn't care when loading and puts ELFOSABI_NONE on core dumps. * Gold and bfd ld produce files with ELFOSABI_NONE. * Gold and bfd ld seems to ignore EI_OSABI other than for freebsd. * Gas puts ELFOSABI_NONE in most .o files. llvm-svn: 248534
* [mips][ias] Implement .cpreturn directive.Daniel Sanders2015-09-221-0/+19
| | | | | | | | | | | | | | | | | Summary: Based on a patch by David Chisnall. I've modified the original patch as follows: * Moved the expansion to the TargetStreamers so that the directive isn't expanded when emitting assembly. * Fixed an operand order bug. * Changed the move instructions from DADDu to OR to match recent changes to GAS. Reviewers: vkalintiris Subscribers: llvm-commits, emaste, seanbruno, theraven Differential Revision: http://reviews.llvm.org/D13017 llvm-svn: 248258
* [mips] Allow constant expressions in second argument of .cpsetup.Daniel Sanders2015-09-211-44/+95
| | | | | | | | | | | | | | Summary: Also tightened up the test and made a trivial fix to prevent double-newline after emitting .cpsetup directives. Reviewers: vkalintiris Subscribers: seanbruno, emaste, llvm-commits Differential Revision: http://reviews.llvm.org/D12956 llvm-svn: 248143
* [mips] Add assembler support for the .cprestore directive.Daniel Sanders2015-09-174-0/+228
| | | | | | | | | | | | | | | | | | Summary: This assembler directive is used in O32 PIC to restore the current function's $gp after executing JAL's. The $gp is first stored on the stack at a user-specified offset. It has the following format: ".cprestore 8" (where 8 is the offset). This fixes llvm.org/PR20967. Patch by Toma Tabacu. Reviewers: seanbruno, tomatabacu Subscribers: brooks, seanbruno, emaste, llvm-commits Differential Revision: http://reviews.llvm.org/D6267 llvm-svn: 247897
* [mips][microMIPS] Implement TEQ, TGE, TGEU, TLT, TLTU and TNE instructionsZoran Jovanovic2015-09-174-1/+72
| | | | | | Differential Revision: http://reviews.llvm.org/D9658 llvm-svn: 247880
* [mips][microMIPS] Implement PREFX, LHUE, LBE, LBUE, LHE, LWE, SBE, SHE and ↵Zoran Jovanovic2015-09-167-2/+30
| | | | | | | | SWE instructions Differential Revision: http://reviews.llvm.org/D9189 llvm-svn: 247780
* [mips] Add support for branch-likely pseudo-instructionsZoran Jovanovic2015-09-154-10/+227
| | | | | | Differential Revision: http://reviews.llvm.org/D10537 llvm-svn: 247697
* [mips][microMIPS] Implement CACHEE and PREFE instructions for microMIPS32r6Zoran Jovanovic2015-09-151-0/+2
| | | | | | Differential Revision: http://reviews.llvm.org/D11632 llvm-svn: 247670
* [mips] Added support for various EVA ASE instructions.Daniel Sanders2015-09-1518-22/+242
| | | | | | | | | | | | | | | | | | | | Summary: Added support for the following instructions: CACHEE, LBE, LBUE, LHE, LHUE, LWE, LLE, LWLE, LWRE, PREFE, SBE, SHE, SWE, SCE, SWLE, SWRE, TLBINV, TLBINVF This required adding some infrastructure for the EVA ASE. Patch by Scott Egerton. Reviewers: vkalintiris, dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D11139 llvm-svn: 247669
* [mips][microMIPS] Implement ADDU16, AND16, ANDI16, NOT16, OR16, SLL16 and ↵Zoran Jovanovic2015-09-091-0/+7
| | | | | | | | SRL16 instructions Differential Revision: http://reviews.llvm.org/D11178 llvm-svn: 247146
* [mips][microMIPS] Implement CACHEE and PREFE instructionsZoran Jovanovic2015-09-091-0/+6
| | | | | | Differential Revision: http://reviews.llvm.org/D11628 llvm-svn: 247125
* [mips][microMIPS] Implement LLE, LUI, LW and LWE instructionsZoran Jovanovic2015-09-081-0/+4
| | | | | | Differential Revision: http://reviews.llvm.org/D1179 llvm-svn: 247017
* [mips][microMIPS] Implement SB, SBE, SCE, SH and SHE instructionsZoran Jovanovic2015-09-081-0/+5
| | | | | | Differential Revision: http://reviews.llvm.org/D11801 llvm-svn: 246999
* [mips][microMIPS] Add microMIPS32r6 and microMIPS64r6 tests for existing ↵Zoran Jovanovic2015-09-084-0/+37
| | | | | | | | 16-bit LBU16, LHU16, LW16, LWGP and LWSP instructions Differential Revision: http://reviews.llvm.org/D10956 llvm-svn: 246987
* [mips][microMIPS] Implement ABS.fmt, CEIL.L.fmt, CEIL.W.fmt, FLOOR.L.fmt, ↵Zoran Jovanovic2015-09-071-1/+18
| | | | | | | | FLOOR.W.fmt, TRUNC.L.fmt, TRUNC.W.fmt, RSQRT.fmt and SQRT.fmt instructions Differential Revision: http://reviews.llvm.org/D11674 llvm-svn: 246968
* [mips][microMIPS] Implement BC16, BEQZC16 and BNEZC16 instructionsZoran Jovanovic2015-09-074-0/+20
| | | | | | Differential Revision: http://reviews.llvm.org/D11181 llvm-svn: 246963
* [mips][microMIPS] Implement CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, ↵Zoran Jovanovic2015-09-072-0/+100
| | | | | | | | MAX.fmt, MIN.fmt, MAXA.fmt, MINA.fmt and CMP.condn.fmt instructions Differential Revision: http://reviews.llvm.org/D12141 llvm-svn: 246960
* [mips][microMIPS] Implement ADD.fmt, SUB.fmt, MOV.fmt, MUL.fmt, DIV.fmt, ↵Zoran Jovanovic2015-09-052-0/+32
| | | | | | | | MADDF.fmt, MSUBF.fmt and NEG.fmt instructions Differential Revision: http://reviews.llvm.org/D11978 llvm-svn: 246919
* [mips] Added support for the div, divu, ddiv and ddivu macros which use ↵Daniel Sanders2015-09-038-0/+329
| | | | | | | | | | | | | | | | traps and breaks in the integrated assembler. Summary: Patch by Scott Egerton Reviewers: vkalintiris, dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D11675 llvm-svn: 246763
* [mips][microMIPS] Add microMIPS32r6 and microMIPS64r6 tests for existing ↵Zoran Jovanovic2015-08-204-0/+32
| | | | | | | | 16-bit ADDIUR1SP, ADDIUR2, ADDIUS5 and ADDIUSP instructions Differential Revision: http://reviews.llvm.org/D10955 llvm-svn: 245554
* [mips] Expand JAL instructions when PIC is enabled.Daniel Sanders2015-08-182-0/+195
| | | | | | | | | | | | | | Summary: This is the correct way to handle JAL instructions when PIC is enabled. Patch by Toma Tabacu Reviewers: seanbruno, tomatabacu Subscribers: brooks, seanbruno, emaste, llvm-commits Differential Revision: http://reviews.llvm.org/D6231 llvm-svn: 245305
* [mips][microMIPS] Implement DDIV, DMOD, DDIVU and DMODU instructionsZoran Jovanovic2015-08-182-0/+31
| | | | | | Differential Revision: http://reviews.llvm.org/D10953 llvm-svn: 245297
* [mips][microMIPS] Implement SW and SWE instructionsZoran Jovanovic2015-08-182-0/+5
| | | | | | Differential Revision: http://reviews.llvm.org/D10869 llvm-svn: 245293
* [mips] [IAS] Add support for the DLA pseudo-instruction and fix problems ↵Daniel Sanders2015-08-175-218/+1251
| | | | | | | | | | | | | | with DLI Summary: It is the same as LA, except that it can also load 64-bit addresses and it only works on 64-bit MIPS architectures. Reviewers: tomatabacu, seanbruno, vkalintiris Subscribers: brooks, seanbruno, emaste, llvm-commits Differential Revision: http://reviews.llvm.org/D9524 llvm-svn: 245208
* [mips] Remap move as or.Vasileios Kalintiris2015-08-1117-42/+50
| | | | | | | | | | | | | | | | | | | | | | | | Summary: This patch remaps the assembly idiom 'move' to 'or' instead of 'daddu' or 'addu'. The use of addu/daddu instead of or as move was highlighted as a performance issue during the analysis of a recent 64bit design. Originally move was encoded as 'or' by binutils but was changed for the r10k cpu family due to their pipeline which had 2 arithmetic units and a single logical unit, and so could issue multiple (d)addu based moves at the same time but only 1 logical move. This patch preserves the disassembly behaviour so that disassembling a old style (d)addu move still appears as move, but assembling move always gives an or Patch by Simon Dardis. Reviewers: vkalintiris Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D11796 llvm-svn: 244579
* [mips] Added support for the ERETNC instruction.Vasileios Kalintiris2015-07-2010-0/+53
| | | | | | | | | | | | | | Summary: This required adding the instruction predicate HasMips32r5. Patch by Scott Egerton. Reviewers: dsanders, vkalintiris Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D11136 llvm-svn: 242666
* [mips] Fix li/la differences between IAS and GAS.Daniel Sanders2015-07-148-86/+381
| | | | | | | | | | | | | | | | | | | Summary: - Signed 16-bit should have priority over unsigned. - For la, unsigned 16-bit must use ori+addu rather than directly use ori. - Correct tests on 32-bit immediates with 64-bit predicates by sign-extending the immediate beforehand. For example, isInt<16>(0xffff8000) should be true and use addiu. Also split li/la testing into separate files due to their size. Reviewers: vkalintiris Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D10967 llvm-svn: 242139
* [mips][microMIPS] Implement SLL and NOP instructionsZoran Jovanovic2015-07-011-0/+2
| | | | | | http://reviews.llvm.org/D10474 llvm-svn: 241150
* [mips] [IAS] Add support for the .module softfloat/hardfloat directives.Toma Tabacu2015-06-302-0/+46
| | | | | | | | | These directives are used to set the default value of the SoftFloat feature. They have the same effect as setting -m{soft, hard}-float from the command line. Differential Revision: http://reviews.llvm.org/D9073 llvm-svn: 241066
* [mips] [IAS] Make .module directives change AssemblerOptions->front().Toma Tabacu2015-06-301-0/+14
| | | | | | Differential Revision: http://reviews.llvm.org/D10643 llvm-svn: 241062
* [mips] [IAS] Add support for the .set oddspreg/nooddspreg directives.Toma Tabacu2015-06-302-0/+20
| | | | | | Differential Revision: http://reviews.llvm.org/D10657 llvm-svn: 241052
* [mips] Add COP0 register class and use it in M[FT]C0/DM[FT]C0.Daniel Sanders2015-06-2711-16/+58
| | | | | | | | | | | | | | | | | Summary: Previously it (incorrectly) used GPR's. Patch by Simon Dardis. A couple small corrections by myself. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D10567 llvm-svn: 240883
* [mips] [IAS] Add partial support for the ULW pseudo-instruction.Toma Tabacu2015-06-264-0/+245
| | | | | | | | | | | | | | | | Summary: This only adds support for ULW of an immediate address with/without a source register. It does not include support for ULW of the address of a symbol. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D9663 llvm-svn: 240782
* [mips] [IAS] Fix parsing of memory offset expressions with parenthesis depth >1.Toma Tabacu2015-06-251-0/+15
| | | | | | | | | | | | | | | | | | | Summary: In an expression such as "(((a+b)+c)+d)", parseParenExpression() would only parse the "a+b)+c", which would result in an error later on in the parser. This means that we can only parse one level of inner parentheses. In order to fix this, I added a new function called parseParenExprOfDepth(), which parses a specified number of trailing parenthesis expressions (except for the outermost parenthesis), and changed MipsAsmParser to use it in parseMemOffset instead of parseParenExpression(). Reviewers: dsanders, rafael Reviewed By: dsanders, rafael Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D9742 llvm-svn: 240625
* [mips][microMIPS] Implement BREAK, EHB and EI instructionsZoran Jovanovic2015-06-242-0/+13
| | | | | | http://reviews.llvm.org/D10090 llvm-svn: 240531
* [mips] [IAS] Add partial support for the ULHU pseudo-instruction.Toma Tabacu2015-06-234-115/+430
| | | | | | | | | | | | | | | | Summary: This only adds support for ULHU of an immediate address with/without a source register. It does not include support for ULHU of the address of a symbol. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D9671 llvm-svn: 240410
* [mips64] Emit correct addend for some PC-relative relocationsPetar Jovanovic2015-06-235-66/+66
| | | | | | | | | | | So far, LLVM has not emitted correct addend for N64 and N32 ABI. This patch fixes that. It also removes fixup from MCJIT for R_MIPS_PC16 relocation. Patch by Vladimir Radosavljevic. Differential Revision: http://reviews.llvm.org/D10565 llvm-svn: 240404
* Revert r240302 ("Bring r240130 back.").Daniel Jasper2015-06-233-9/+9
| | | | | | | | | | | | | This causes errors like: ld: error: blah.o: requires dynamic R_X86_64_PC32 reloc against '' which may overflow at runtime; recompile with -fPIC blah.cc:function f(): error: undefined reference to '' blah.o:g(): error: undefined reference to '' I have not yet come up with an appropriate reproduction. llvm-svn: 240394
* [mips] llvm-readobj can parse .MIPS.abiflags. No need to check the bytes.Daniel Sanders2015-06-232-13/+35
| | | | | | | | | | | | | | Summary: Reviewers: atanasyan Reviewed By: atanasyan Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D10538 llvm-svn: 240392
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