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* [mips][micromips] Written missing test for CEIL.L.S, CEIL.L.D, FLOOR.L.S and ↵Hrvoje Varga2016-02-121-0/+4
| | | | | | | | FLOOR.L.D instructions Differential Revision: http://reviews.llvm.org/D17192 llvm-svn: 260673
* [MC] Fixed parsing of macro arguments where expressions with spaces are present.Scott Egerton2016-02-111-0/+40
| | | | | | | | | | | | | | | Summary: Fixed an issue for mips with an instruction such as 'sdc1 $f1, 272 +8(a0)' which has a space between '272' and '+'. The parser would then parse '272' and '+8' as two arguments instead of a single expression resulting in one too many arguments in the pseudo instruction. The reason that the test case has been changed is so that the expected output matches the output of the GNU assembler. Reviewers: vkalintiris, dsanders Subscribers: dsanders, llvm-commits Differential Revision: http://reviews.llvm.org/D13592 llvm-svn: 260521
* [mips] Extend MipsAsmParser class to handle %got(sym + const) expressionsSimon Atanasyan2016-02-091-0/+20
| | | | | | | | | Now the parser supports `%got(sym)` expressions only but `%got(sym + const)` variant is also valid and accepted by GAS. Differential Revision: http://reviews.llvm.org/D16885 llvm-svn: 260305
* [mips] Range check uimm16 and fix several bugs this revealed.Daniel Sanders2016-02-018-33/+83
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: The bugs were: * teq and similar take 4-bit unsigned immediates on microMIPS. * teqi and similar have side-effects like teq do. * shll_s.w and shra_r.w take 5-bit unsigned immediates. * The various DSP ext* instructions take a 5-bit immediate. * repl.qh takes an 8-bit unsigned immediate. * repl.ph takes a 10-bit unsigned immediate. * rddsp/wrdsp take a 10-bit unsigned immediate. * teqi and similar take signed 16-bit immediates (10-bit for microMIPS). * Out-of-range immediate macros for or/xor take a simm32/simm64 depending on architecture. I'll fix the simm64 case properly when I reach simm32. lui is a bit more lenient than GAS and accepts signed immediates in addition to unsigned. This is because MipsMCExpr can produce signed values when constant folding and it currently lacks a way of knowing it should fold to an unsigned value. Reviewers: vkalintiris Subscribers: dsanders, llvm-commits Differential Revision: http://reviews.llvm.org/D15446 llvm-svn: 259360
* [mips] Absolute value macro expansionZoran Jovanovic2016-01-291-0/+12
| | | | | | | | Author: obucina Reviewers: dsanders Differential Revision: http://reviews.llvm.org/D16323 llvm-svn: 259202
* [mips] Allowed dla instructions on 32-bit architectures.Scott Egerton2016-01-211-0/+228
| | | | | | | | | | | | | | | Summary: This is now the same as the behaviour of the GNU assembler. This was done as it is required in order to build the Linux kernel with the integrated assembler enabled. Reviewers: dsanders, vkalintiris Subscribers: dsanders, llvm-commits Differential Revision: http://reviews.llvm.org/D13594 llvm-svn: 258400
* [MC, COFF] Add .reloc support for WinCOFFDavid Majnemer2016-01-191-0/+6
| | | | | | | This adds rudimentary support for a few relocations that we will use for the CodeView debug format. llvm-svn: 258216
* [mips] Never select JAL for calls to an absolute immediate address.Daniel Sanders2016-01-1115-0/+15
| | | | | | | | | | | | | | | Summary: It actually takes an offset into the current PC-region. This fixes the 'expr' command in lldb. Reviewers: vkalintiris, jaydeep, bhushan Subscribers: dsanders, llvm-commits Differential Revision: http://reviews.llvm.org/D16054 llvm-svn: 257339
* [mips][microMIPS] Implement DERET and DI instructions and check size operand ↵Zlatko Buljan2015-12-217-9/+46
| | | | | | | | for EXT and DEXT* instructions Differential Revision: http://reviews.llvm.org/D15570 llvm-svn: 256152
* [mips][microMIPS][DSP] Implement PACKRL.PH, PICK.PH, PICK.QB, SHILO, SHILOV ↵Zlatko Buljan2015-12-1811-0/+45
| | | | | | | | and WRDSP instructions Differential Revision: http://reviews.llvm.org/D14429 llvm-svn: 255991
* [mips][ias] Range check uimm10 operandsDaniel Sanders2015-12-095-15/+26
| | | | | | | | | | | | Summary: Reviewers: vkalintiris Subscribers: dsanders, llvm-commits Differential Revision: http://reviews.llvm.org/D15229 llvm-svn: 255112
* Revert r254897 "[mips][microMIPS] Implement LH, LHE, LHU and LHUE instructions"Zlatko Buljan2015-12-097-68/+0
| | | | | | | | | Commited patch was intended to implement LH, LHE, LHU and LHUE instructions. After commit test-suite failed with error message in the form of: fatal error: error in backend: Cannot select: t124: i32,ch = load<LD2[%d](tbaa=<0x94acc48>), sext from i16> t0, t2, undef:i32 For that reason I decided to revert commit r254897 and make new patch which besides implementation and standard regression tests will also have dedicated tests (CodeGen) for the above error. llvm-svn: 255109
* [mips][ias] Range check uimm8 operandsDaniel Sanders2015-12-082-0/+9
| | | | | | | | | | | | Summary: Reviewers: vkalintiris Subscribers: llvm-commits, dsanders Differential Revision: http://reviews.llvm.org/D15226 llvm-svn: 255018
* [mips][ias] Range check uimm6 operands and fix a bug this revealed.Daniel Sanders2015-12-086-1/+123
| | | | | | | | | | | | | | | | | Summary: We don't check the size operand on ext/dext*/ins/dins* yet because the permitted range depends on the pos argument and we can't check that using this mechanism. The bug was that dextu/dinsu accepted 0..31 in the pos operand instead of 32..63. Reviewers: vkalintiris Subscribers: llvm-commits, dsanders Differential Revision: http://reviews.llvm.org/D15190 llvm-svn: 255015
* [mips][ias] Removed DSP/DSPr2 instructions from base architecture ↵Daniel Sanders2015-12-078-765/+255
| | | | | | | | | | | | | | | | | valid-xfail.s's. Summary: valid-xfail.s is for instructions that should be valid in the given ISA but incorrectly fail. DSP/DSPr2 instructions are correct to fail since DSP/DSPr2 is not enabled. Reviewers: vkalintiris Subscribers: dsanders, llvm-commits Differential Revision: http://reviews.llvm.org/D15072 llvm-svn: 254911
* [mips][microMIPS] Implement LH, LHE, LHU and LHUE instructionsZlatko Buljan2015-12-077-0/+68
| | | | | | Differential Revision: http://reviews.llvm.org/D9824 llvm-svn: 254897
* [mips][DSP] Add DSPr1 and DSPr2 tests for the standard encodingsZlatko Buljan2015-12-032-45/+299
| | | | | | Differential Revision: http://reviews.llvm.org/D15141 llvm-svn: 254598
* [mips][microMIPS] Implement PREPEND, RADDU.W.QB, RDDSP, REPL.PH, REPL.QB, ↵Hrvoje Varga2015-12-022-0/+8
| | | | | | | | REPLV.PH, REPLV.QB and MTHLIP instructions Differential Revision: http://reviews.llvm.org/D14527 llvm-svn: 254496
* [mips][microMIPS] Implement RECIP.fmt, RINT.fmt, ROUND.L.fmt, ROUND.W.fmt, ↵Hrvoje Varga2015-12-012-0/+32
| | | | | | | | SEL.fmt, SELEQZ.fmt, SELNEQZ.fmt and CLASS.fmt Differential Revision: http://reviews.llvm.org/D13885 llvm-svn: 254405
* [mips][microMIPS] Implement LBUX, LHX, LWX, MAQ_S[A].W.PHL, MAQ_S[A].W.PHR, ↵Hrvoje Varga2015-11-301-0/+11
| | | | | | | | MFHI, MFLO, MTHI and MTLO instructions Differential Revision: http://reviews.llvm.org/D14436 llvm-svn: 254297
* [mips][microMIPS] Fix issue with offset operand of BALC and BC instructionsZoran Jovanovic2015-11-301-2/+2
| | | | | | | Value of offset operand for microMIPS BALC and BC instructions is currently shifted 2 bits, but it should be 1 bit. Differential Revision: http://reviews.llvm.org/D14770 llvm-svn: 254296
* [mips][ias] Removed MSA instructions from base architecture valid-xfail.s's.Daniel Sanders2015-11-307-330/+62
| | | | | | | valid-xfail.s is for instructions that should be valid in the given ISA but incorrectly fail. MSA instructions are correct to fail since MSA is not enabled. llvm-svn: 254293
* [mips][microMIPS] Implement PRECR.QB.PH, PRECR_SRA[_R].PH.W, PRECRQ.PH.W, ↵Zlatko Buljan2015-11-302-0/+11
| | | | | | | | PRECRQ.QB.PH, PRECRQU_S.QB.PH and PRECRQ_RS.PH.W instructions Differential Revision: http://reviews.llvm.org/D14605 llvm-svn: 254291
* [mips][ias] Range check uimm5 operands and fix several bugs this revealed.Daniel Sanders2015-11-2618-58/+185
| | | | | | | | | | | | | | | | | | | | | | | | Summary: The bugs were: * append, prepend, and balign were not tested * balign takes a uimm2 not a uimm5. * drotr32 was correctly implemented with a uimm5 but the tests expected '52' to be valid. * li/la were implemented with a uimm5 instead of simm32. simm32 isn't completely correct either but I'll fix that when I get to simm32. A notable omission are some of the shift instructions. Several of these have been implemented using a single uimm6 instruction (rather than two uimm5 instructions and a CodeGen-only uimm6 pseudo). These will be updated in the uimm6 patch. Reviewers: vkalintiris Subscribers: llvm-commits, dsanders Differential Revision: http://reviews.llvm.org/D14712 llvm-svn: 254164
* [mips] .ent and .end should also set the type and size of the symbol ↵Daniel Sanders2015-11-231-0/+50
| | | | | | | | | | | | respectively. Reviewers: vkalintiris Subscribers: llvm-commits, seanbruno, emaste, vkalintiris, dsanders Differential Revision: http://reviews.llvm.org/D14221 llvm-svn: 253875
* [mips][microMIPS] Implement MUL[_S].PH, MULEQ_S.W.PHL, MULEQ_S.W.PHR, ↵Hrvoje Varga2015-11-202-0/+15
| | | | | | | | MULEU_S.PH.QBL, MULEU_S.PH.QBR, MULQ_RS.PH, MULQ_RS.W, MULQ_S.PH and MULQ_S.W instructions Differential Revision: http://reviews.llvm.org/D14280 llvm-svn: 253651
* [mips] Add tests for ROL and ROR macros expansionZoran Jovanovic2015-11-193-0/+356
| | | | | Author: obucina llvm-svn: 253567
* [mips][microMIPS] Implement DPS.W.PH, DPSQ_S.W.PH, DPSQ_SA.L.W, ↵Hrvoje Varga2015-11-182-0/+12
| | | | | | | | DPSQX_S.W.PH, DPSQX_SA.W.PH, DPSU.H.QBL, DPSU.H.QBR and DPSX.W.PH instructions Differential Revision: http://reviews.llvm.org/D14058 llvm-svn: 253443
* [mips][microMIPS] Implement EXTP, EXTPDP, EXTPDPV, EXTPV, EXTR[_RS].W, ↵Zlatko Buljan2015-11-172-0/+24
| | | | | | | | EXTR_S.H, EXTRV[_RS].W and EXTRV_S.H instructions Differential Revision: http://reviews.llvm.org/D14174 llvm-svn: 253332
* [mips][microMIPS] Implement SUBQ[_S].PH, SUBQ_S.W, SUBQH[_R].PH, ↵Zlatko Buljan2015-11-172-0/+18
| | | | | | | | SUBQH[_R].W, SUBU[_S].PH, SUBU[_S].QB and SUBUH[_R].QB instructions Differential Revision: http://reviews.llvm.org/D14114 llvm-svn: 253329
* [Assembler] Make fatal assembler errors non-fatalOliver Stannard2015-11-174-4/+10
| | | | | | | | | | | | | | Currently, if the assembler encounters an error after parsing (such as an out-of-range fixup), it reports this as a fatal error, and so stops after the first error. However, for most of these there is an obvious way to recover after emitting the error, such as emitting the fixup with a value of zero. This means that we can report on all of the errors in a file, not just the first one. MCContext::reportError records the fact that an error was encountered, so we won't actually emit an object file with the incorrect contents. Differential Revision: http://reviews.llvm.org/D14717 llvm-svn: 253328
* [Assembler] Allow non-fatal errors after parsingOliver Stannard2015-11-172-2/+2
| | | | | | | | | | | | | | | | | This adds reportError to MCContext, which can be used as an alternative to reportFatalError when the assembler wants to try to continue processing the rest of the file after the error is reported, so that all of the errors ina file can be reported. It records the fact that an error was encountered, so we can avoid emitting an object file if any errors occurred. This patch doesn't add any uses of this function (a later patch will convert most uses of reportFatalError to use it), but there is a small functional change: we use the SourceManager to print the error message, even if we have a null SMLoc. This means that we get a SourceManager-style message, with the file and line information shown as <unknown>, rather than the "LLVM ERROR" style used by report_fatal_error. llvm-svn: 253327
* [mips][microMIPS] Implement PRECEQ.W.PHL, PRECEQ.W.PHR, PRECEQU.PH.QBL, ↵Zlatko Buljan2015-11-172-0/+20
| | | | | | | | PRECEQU.PH.QBLA, PRECEQU.PH.QBR, PRECEQU.PH.QBRA, PRECEU.PH.QBL, PRECEU.PH.QBLA, PRECEU.PH.QBR and PRECEU.PH.QBRA instructions Differential Revision: http://reviews.llvm.org/D14279 llvm-svn: 253326
* Added microMIPSDSPr1 assembler and disassembler tests to existing ↵Zlatko Buljan2015-11-172-3/+39
| | | | | | microMIPSDSPr2 test files. llvm-svn: 253320
* [mips][microMIPS] Implement SHRA[_R].PH, SHRAV[_R].PH, SHRAV[_R].QB, ↵Zlatko Buljan2015-11-136-0/+72
| | | | | | | | SHRAV_R.W, SHRA_R.W, SHRL.PH, SHRL.QB, SHRLV.PH and SHRLV.QB instructions Differential Revision: http://reviews.llvm.org/D14010 llvm-svn: 253041
* Implement .reloc (constant offset only) with support for R_MIPS_NONE and ↵Daniel Sanders2015-11-122-0/+64
| | | | | | | | | | | | | | | | R_MIPS_32. Summary: Support for R_MIPS_NONE allows us to parse MIPS16's usage of .reloc. R_MIPS_32 was included to be able to better test the directive. Targets can add their relocations by overriding MCAsmBackend::getFixupKind(). Subscribers: grosbach, rafael, majnemer, dsanders, llvm-commits Differential Revision: http://reviews.llvm.org/D13659 llvm-svn: 252888
* [mips][microMIPS] Implement LWM16, SB16, SH16, SW16, SWSP and SWM16 instructionsZlatko Buljan2015-11-124-0/+74
| | | | | | Differential Revision: http://reviews.llvm.org/D11406 llvm-svn: 252885
* [mips] Move MC tests for the DSP ASE into the standard format.Daniel Sanders2015-11-112-97/+45
| | | | | | | | | | | | | | Summary: Only DSPr2 is present because it appears we've never added DSPr1 tests. We'll have to correct that in a later patch. Reviewers: vkalintiris Subscribers: llvm-commits, dsanders Differential Revision: http://reviews.llvm.org/D14448 llvm-svn: 252752
* [mips][ias] Range check uimm4 operands and fixed a bug this revealed.Daniel Sanders2015-11-063-0/+31
| | | | | | | | | | | | | | | Summary: The bug was that the sldi instructions have immediate widths dependant on their element size. So sldi.d has a 1-bit immediate and sldi.b has a 4-bit immediate. All of these were using 4-bit immediates previously. Reviewers: vkalintiris Subscribers: llvm-commits, atanasyan, dsanders Differential Revision: http://reviews.llvm.org/D14018 llvm-svn: 252297
* [mips][ias] Range check uimm3 operands.Daniel Sanders2015-11-064-0/+20
| | | | | | | | | | | | Summary: Reviewers: vkalintiris Subscribers: atanasyan, dsanders, llvm-commits Differential Revision: http://reviews.llvm.org/D14016 llvm-svn: 252296
* [mips][ias] Range check uimm2 operands and fix a bug this revealed.Daniel Sanders2015-11-069-5/+29
| | | | | | | | | | | | | | | Summary: The bug was that the MIPS32R6/MIPS64R6/microMIPS32R6 versions of LSA and DLSA (unlike the MSA version) failed to account for the off-by-one encoding of the immediate. The range is actually 1..4 rather than 0..3. Reviewers: vkalintiris Subscribers: atanasyan, dsanders, llvm-commits Differential Revision: http://reviews.llvm.org/D14015 llvm-svn: 252295
* [mips][ias] Range check uimmz operands.Daniel Sanders2015-11-062-0/+22
| | | | | | | | | | Reviewers: vkalintiris Subscribers: dsanders, atanasyan, llvm-commits Differential Revision: http://reviews.llvm.org/D14013 llvm-svn: 252294
* Relax a few more overspecified tests.Rafael Espindola2015-11-031-1/+1
| | | | llvm-svn: 251967
* [mips][microMIPS] Implement PAUSE, RDHWR, RDPGPR, SDBBP, SSNOP, SYNC, SYNCI ↵Hrvoje Varga2015-10-282-8/+21
| | | | | | | | and WAIT instructions Differential Revision: http://reviews.llvm.org/D12628 llvm-svn: 251510
* [mips][microMIPS] Implement SHLL.PH, SHLL_S.PH, SHLL.QB, SHLLV.PH, ↵Zlatko Buljan2015-10-232-0/+10
| | | | | | | | SHLLV_S.PH, SHLLV.QB, SHLLV_S.W, SHLL_S.W, SHRA.QB and SHRA_R.QB instructions Differential Revision: http://reviews.llvm.org/D13929 llvm-svn: 251098
* [mips][msa] Remove copy_u.d and move copy_u.w to MSA64.Daniel Sanders2015-10-212-36/+15
| | | | | | | | | | | | | | | | | | | | | | | Summary: The forwards compatibility strategy employed by MIPS is to consider registers to be infinitely sign-extended. Then on ISA's with a wider register, the result of existing instructions are sign-extended to register width and zero-extended counterparts are added. copy_u.w on MSA32 and copy_u.w on MSA64 violate this strategy and we have therefore corrected the MSA specs to fix this. We still keep track of sign/zero-extension during legalization but we now match copy_s.[wd] where required. No change required to clang since __builtin_msa_copy_u_[wd] will map to copy_s.[wd] where appropriate for the target. Reviewers: vkalintiris Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D13472 llvm-svn: 250887
* [mips][microMIPS] Implement ADDQ.PH, ADDQ_S.W, ADDQH.PH, ADDQH.W, ADDSC, ↵Zlatko Buljan2015-10-192-0/+14
| | | | | | | | ADDU.PH, ADDU_S.QB, ADDWC and ADDUH.QB instructions Differential Revision: http://reviews.llvm.org/D13130 llvm-svn: 250685
* [mips][microMIPS] Implement ABSQ.QB, ABSQ_S.PH, ABSQ_S.W, ABSQ_S.QB, INSV, ↵Zlatko Buljan2015-10-192-0/+10
| | | | | | | | MADD, MADDU, MSUB, MSUBU, MULT and MULTU instructions Differential Revision: http://reviews.llvm.org/D13721 llvm-svn: 250683
* Commited two test files which are forgotten during commit of patch for ↵Zlatko Buljan2015-10-161-0/+7
| | | | | | http://reviews.llvm.org/D13376 llvm-svn: 250512
* [mips][microMIPS] Implement LB, LBE, LBU and LBUE instructionsHrvoje Varga2015-10-161-0/+4
| | | | | | Differential Revision: http://reviews.llvm.org/D11633 llvm-svn: 250511
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