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* [mips] Remove CPU-only triples from llvm-objdump commands.Daniel Sanders2016-06-036-10/+9
| | | | | | | | | | | | Summary: They aren't necessary since llvm-objdump can auto-detect the architecture. Reviewers: sdardis Subscribers: jfb, dsanders, llvm-commits, sdardis Differential Revision: http://reviews.llvm.org/D20904 llvm-svn: 271653
* [mips] Implement 'la' macro in PIC mode for O32.Daniel Sanders2016-06-031-0/+54
| | | | | | | | | | | | | | | | Summary: N32 support will follow in a later patch since the symbol version of 'la' incorrectly believes N32 to have 64-bit pointers and rejects it early. This fixes the three incorrectly expanded 'la' macros found in bionic. Reviewers: sdardis Subscribers: dsanders, llvm-commits, sdardis Differential Revision: http://reviews.llvm.org/D20820 llvm-svn: 271644
* [mips] Remove tests which should have been deleted.Simon Dardis2016-05-312-38/+0
| | | | | | | The two xfail tests for mis32r6 & mips64r6 were supposed to be removed in r271301. llvm-svn: 271306
* [mips] Enforce compact branch register restrictionsSimon Dardis2016-05-314-20/+52
| | | | | | | | | | | | | | | Enforce compact branch register restrictions such as the use of the zero register, both operands being the same register. Emit clear error in such cases as the issue is subtle. For bovc and bnvc, silently fixup such cases when emitting objects directly, like LLVM started doing in rL269899. Reviewers: vkalintiris, dsanders Differential Review: http://reviews.llvm.org/D20475 llvm-svn: 271301
* [mips] Weaken asm predicate for memory offsetsSimon Dardis2016-05-2715-0/+400
| | | | | | | | | | | | The isMemWithSimmOffset predicate rejects relocations which is incorrect behaviour. Linkers and other tools should handle|warn|error when the field overflows. Reviewers: dsanders, vkalintiris Differential Revision: http://reviews.llvm.org/D20727 llvm-svn: 270995
* ps][microMIPS] Add R_MICROMIPS_PC21_S1 relocationZoran Jovanovic2016-05-192-0/+20
| | | | | | Differential Revision: http://reviews.llvm.org/D15526 llvm-svn: 270048
* [mips][microMIPS] Implement BC1EQZC, BC1NEZC, BC2EQZC and BC2NEZC instructionsZlatko Buljan2016-05-194-0/+48
| | | | | | Differential Revision: http://reviews.llvm.org/D18352 llvm-svn: 270030
* Don't pass a Reloc::Model to MC.Rafael Espindola2016-05-185-19/+19
| | | | | | | | | | | | MC only needs to know if the output is PIC or not. It never has to decide about creating GOTs and PLTs for example. The only thing that MC itself uses this information for is expanding "macros" in sparc and mips. The rest I am pretty sure could be moved to CodeGen. This is a cleanup and isolates the code from future changes to Reloc::Model. llvm-svn: 269909
* [mips][microMIPS] Implement LH, LHE, LHU and LHUE instructions and add ↵Zlatko Buljan2016-05-187-0/+88
| | | | | | | | CodeGen support Differential Revision: http://reviews.llvm.org/D15418 llvm-svn: 269883
* Don't pass relocation-model= to tests that don't need it.Rafael Espindola2016-05-185-6/+6
| | | | | | | Very few things in MC itself use the option. Most of the code that that uses it could be move to CodeGen. llvm-svn: 269871
* [mips][microMIPS] Implement BEQZC and BNEZC instructionsZoran Jovanovic2016-05-171-0/+2
| | | | | | Differential Revision: http://reviews.llvm.org/D15417 llvm-svn: 269755
* [mips][microMIPS][DSP] Implement BALIGN, BITREV, BPOSGE32, CMP*, CMPGDU*, ↵Zlatko Buljan2016-05-177-0/+38
| | | | | | | | CMPGU* and CMPU* instructions Differential Revision: http://reviews.llvm.org/D16182 llvm-svn: 269752
* [mips][ias] Fix R_MICROMIPS_GOT16 evaluation and eliminate symbol for ↵Daniel Sanders2016-05-161-1/+80
| | | | | | | | | | | | | | | | | | | R_MICROMIPS_(GOT|HI|LO)16 Summary: The failure r269410 worked around turned out to be caused by an incorrect evaluation of R_MICROMIPS_GOT16 which then caused the GOT entries to be incorrect. This patch fixes the evaluation and reverts r269410. Reviewers: sdardis, vkalintiris, rafael Subscribers: rafael, dsanders, sdardis, llvm-commits Differential Revision: http://reviews.llvm.org/D20242 llvm-svn: 269641
* [mips][ias] EF_MIPS_MICROMIPS should iff microMIPS code was emitted.Daniel Sanders2016-05-162-1/+17
| | | | | | | | | | | | | | | Summary: This fixes PR27682. Additionally, '.set micromips' by itself is not sufficient to raise the EF_MIPS_MICROMIPS flag. It is also necessary to emit a microMIPS instruction. This has also been fixed. Reviewers: sdardis, vkalintiris, rafael Subscribers: rafael, dsanders, sdardis, llvm-commits Differential Revision: http://reviews.llvm.org/D20214 llvm-svn: 269639
* [mips] Addition of a third operand to the instructions [d]div, [d]divuZoran Jovanovic2016-05-168-34/+192
| | | | | | | | | Author: obucina Reviewers: dsanders Adds support for third operand for [D]DIV[U] instructions. Additional test for case when destination reg is zero register Differential Revision: http://reviews.llvm.org/D16888 llvm-svn: 269636
* [mips][ias] Work around yet another incorrect microMIPS relocation ↵Daniel Sanders2016-05-131-1/+3
| | | | | | | | | | | | evaluation exposed by r268900. It's not entirely clear why R_MICROMIPS_(GOT|HI16|LO16) are evaluated incorrectly in a small number of the LNT tests at this point. However, it's not related to the STO_MIPS_MICROMIPS issue. At this point all the microMIPS-related changes of r268900 have been reverted. llvm-svn: 269410
* [mips][microMIPS] Implement APPEND, BPOSGE32C, MODSUB, MULSA.W.PH and ↵Hrvoje Varga2016-05-134-0/+14
| | | | | | | | MULSAQ_S.W.PH instructions Differential Revision: http://reviews.llvm.org/D14117 llvm-svn: 269408
* [mips][ias] Fix O32 .cprestore directive when inside .set noat region and ↵Daniel Sanders2016-05-121-1/+20
| | | | | | | | | | | | | | | | | | offset is in range. Summary: This expands on r269179 to fix an additional case that was not covered by our tests. The assembler temporary is not needed when the .cprestore offset fits inside a simm16 and it is not an error to use it inside a '.set noat' in this case. Reviewers: emaste, seanbruno, sdardis Subscribers: dsanders, sdardis, llvm-commits Differential Revision: http://reviews.llvm.org/D20199 llvm-svn: 269295
* [mips][ias] Work around incorrect another microMIPS relocation evaluation ↵Daniel Sanders2016-05-121-0/+9
| | | | | | | | | | | | | | | | | | | | exposed by r268900 As explained in r269196, microMIPS has a special case that is not correctly implemented in LLVM. If we have a symbol 'foo' which is equivalent to '.text+0x10'. The value of an R_MICROMIPS_LO16 relocation using 'foo' is 'foo+0x11' and not 'foo+0x10'. The in-place addend should therefore be 0x11. This commit reverts a little more of the effect of r268900 by keeping the symbol when the STO_MIPS_MICROMIPS flag is set for R_MIPS_GPREL32 relocations. This fixes SingleSource/UnitTests/2003-08-11-VaListArg, and SingleSource/UnitTests/2003-05-07-VarArgs for microMIPS. I believe there are additional relocations that have the same issue (e.g. R_MIPS_64, and R_MIPS_GPREL16) but for now I'm focusing on restoring our internal buildbots back to the green state we had in r268899. llvm-svn: 269294
* Revert "[mips][microMIPS] Implement CFC*, CTC* and LDC* instructions"Hrvoje Varga2016-05-125-20/+7
| | | | | | This reverts commit r269176 as it caused test-suite failure. llvm-svn: 269287
* [mips][ias] Correct ELF eflags when Octeon is the target.Daniel Sanders2016-05-122-12/+31
| | | | | | | | | | Reviewers: sdardis Subscribers: petarj, mpf, dsanders, spetrovic, llvm-commits, sdardis Differential Revision: http://reviews.llvm.org/D18899 llvm-svn: 269283
* [mips][ias] Handle N64 compound relocations and R_MIPS_SUB in ↵Daniel Sanders2016-05-122-10/+45
| | | | | | | | | | | | | | | | | | | needsRelocateWithSymbol() Summary: This eliminates the default case for N64 that was left out of r269047. The change to R_MIPS_SUB is needed in this patch to make this testable since %lo(%neg(%gp_rel(foo))) and %hi(%neg(%gp_rel(foo))) remain the only ways to get a compound relocation from the assembler. Reviewers: sdardis, rafael Subscribers: dsanders, llvm-commits, sdardis Differential Revision: http://reviews.llvm.org/D20097 llvm-svn: 269280
* [mips][ias] Work around incorrect microMIPS relocation evaluation exposed by ↵Daniel Sanders2016-05-111-0/+20
| | | | | | | | | | | | | | | r268900 microMIPS has a special case that is not correctly implemented in LLVM. If we have a symbol 'foo' which is equivalent to '.text+0x10'. The value of an R_MICROMIPS_LO16 relocation using 'foo' is 'foo+0x11' and not 'foo+0x10'. The in-place addend should therefore be 0x11. Work around this by partially reverting the effect of r268900 by keeping the symbol when the STO_MIPS_MICROMIPS flag is set. This fixes SingleSource/Regression/C/PR640 for microMIPS. llvm-svn: 269196
* [mips][ias] Fix N32 and N64 .cprestore directive when inside .set noat region.Daniel Sanders2016-05-111-0/+36
| | | | | | | | | | | | | | | | | | Summary: r268058 unintentionally made the retrieval of the current assembler temporary unconditional. This was fine for the existing tests but it broke the cases where the assembler temporary is not needed (N32/N64 or not PIC) and is unavailable due to a '.set noat' directive. This fixes FreeBSD's libc. Reviewers: emaste, sdardis, seanbruno Subscribers: dsanders, emaste, sdardis, llvm-commits Differential Revision: http://reviews.llvm.org/D20093 llvm-svn: 269179
* [mips][microMIPS] Implement CFC*, CTC* and LDC* instructionsHrvoje Varga2016-05-115-7/+20
| | | | | | Differential Revision: http://reviews.llvm.org/D19713 llvm-svn: 269176
* [mips][micromips] Implement DSBH, DSHD, DSLL, DSLL32, DSLLV, DSRA, DSRA32 ↵Hrvoje Varga2016-05-112-0/+16
| | | | | | | | and DSRAV instructions Differential Revision: http://reviews.llvm.org/D16800 llvm-svn: 269169
* [mips][ias] Make the default path unreachable in needsRelocateWithSymbol() ↵Daniel Sanders2016-05-101-6/+6
| | | | | | | | | | | | | | | (except for N64). Following post-commit comments on r268900 from Rafael Espindola: The missing relocations are now explicitly listed in the switch statement with appropriate FIXME comments and the default path is now unreachable. The temporary exception to this is that compound relocations for N64 still have a default path that returns true. This is because fixing that case ought to be a separate patch. Also make R_MIPS_NONE return false since it has no effect on the section data. llvm-svn: 269047
* [mips][ias] R_MIPS_(GOT|HI|LO|PC)16 and R_MIPS_GPREL32 do not need symbols.Daniel Sanders2016-05-093-43/+101
| | | | | | | | | | | | | | | | | Summary: In theory, care must be taken to ensure that pairs of R_MIPS_(GOT|HI|LO)16 make the same decision on both relocs in the reloc pair but in practice this isn't as hard as it sounds and only limits the complexity of the predicate used. We handle all three with the same code to ensure their decisions always agree with each other. Reviewers: sdardis Subscribers: rafael, dsanders, sdardis, llvm-commits Differential Revision: http://reviews.llvm.org/D19016 llvm-svn: 268900
* [mips][microMIPS] Implement LWP and SWP instructionsZlatko Buljan2016-05-095-0/+28
| | | | | | Differential Revision: http://reviews.llvm.org/D10640 llvm-svn: 268896
* [mips] Fix inconsistent .cprestore behaviour between direct object emission ↵Daniel Sanders2016-05-061-0/+12
| | | | | | | | | | | | | | | | | | | and assembling. Summary: Direct object emission has an initialization order problem where an InitMCObjectFile is called after MipsTargetELFStreamer determines whether PIC is enabled by default or not. There doesn't seem to be point that initializes all cases so split the responsibility between MipsTargetELFStreamer and MipsAsmPrinter. Reviewers: sdardis Subscribers: dsanders, llvm-commits, sdardis Differential Revision: http://reviews.llvm.org/D19728 llvm-svn: 268737
* [mips] Correct the ordering of HI/LO pairs in the relocation table.Daniel Sanders2016-05-061-109/+382
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: There seems to have been a misunderstanding as to the meaning of 'offset' in the rules laid down by our ABI. The previous code believed that 'offset' meant the offset within the section that the relocation is applied to. However, it should have meant the offset from the symbol used in the relocation expression. This patch adds two fields to ELFRelocationEntry and uses them to correct the order of relocations for MIPS. These fields contain: * The original symbol before shouldRelocateWithSymbol() is considered. This ensures that R_MIPS_GOT16 is able to correctly distinguish between local and external symbols, allowing us to tell whether %got() requires a matching %lo() or not (local symbols require one, external symbols don't). It also prevents confusing cases where the fuzzy matching rules cause things like %hi(foo)/%lo(foo+3) and %hi(bar)/%lo(bar+1) to swap their %lo()'s. * The original offset before shouldRelocateWithSymbol() is considered. The existing Addend field is always zero when the object uses in place addends (because it's already moved it to the encoding) but MIPS needs to use the original offset to ensure that the linker correctly calculates the carry-in bit for %hi() and %got(). IAS ensures that unmatchable %hi()/%got() relocations are placed at the end of the table to ensure that the linker rejects the table (we're unable to report such errors directly). The alternatives to this risk accidental matching against inappropriate relocations which may silently compute incorrect values due to an incorrect carry bit between the %lo() and %hi()/%got(). Reviewers: sdardis Subscribers: dsanders, sdardis, rafael, llvm-commits Differential Revision: http://reviews.llvm.org/D19718 llvm-svn: 268733
* [mips][microMIPS] Add CodeGen support for MUL* and DMUL* instructionsZlatko Buljan2016-05-061-0/+8
| | | | | | Differential Revision: http://reviews.llvm.org/D15744 llvm-svn: 268714
* Fix Mips Parser error reportingNirav Dave2016-05-051-1/+8
| | | | | | | | | | | | | [mips] On error, ParseDirective should always return false to signify that the directive was understood. Reviewers: dsanders, vkalintiris, sdardis Subscribers: dsanders, llvm-commits, sdardis Differential Revision: http://reviews.llvm.org/D19929 llvm-svn: 268630
* [mips][ias] Only round section sizes when explicitly requested.Daniel Sanders2016-05-041-2/+2
| | | | | | | | As requested by Rafael Espindola in his post-commit comments on r268036. This makes the previous behaviour the default while still allowing verification of IAS. llvm-svn: 268496
* [mips][microMIPS] Add CodeGen support for microMIPSr6 ROTR and ROTRV and add ↵Zlatko Buljan2016-05-048-0/+87
| | | | | | | | tests for LL, SC, SYSCALL, ROTR, ROTRV, LWM32, SWM32 and MOVEP instructions Differential Revision: http://reviews.llvm.org/D19857 llvm-svn: 268491
* [mips] Use MipsMCExpr instead of MCSymbolRefExpr for all relocations.Daniel Sanders2016-05-0312-134/+134
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This is much closer to the way MIPS relocation expressions work (%hi(foo + 2) rather than %hi(foo) + 2) and removes the need for the various bodges in MipsAsmParser::evaluateRelocExpr(). Removing those bodges ensures that the constant stored in MCValue is the full 32 or 64-bit (depending on ABI) offset from the symbol. This will be used to correct the %hi/%lo matching needed to sort the relocation table correctly. As part of this: * Gave MCExpr::print() the ability to omit parenthesis when emitting a symbol reference inside a MipsMCExpr operator like %hi(X). Without this we print things like %lo(($L1)). * %hi(%neg(%gprel(X))) is now three MipsMCExpr's instead of one. Most of the related special cases have been removed or moved to MipsMCExpr. We can remove the rest as we gain support for the less common relocations when they are not part of this specific combination. * Renamed MipsMCExpr::VariantKind and the enum prefix ('VK_') to avoid confusion with MCSymbolRefExpr::VariantKind and its prefix (also 'VK_'). * fixup_Mips_GOT_Local and fixup_Mips_GOT_Global were found to be identical and merged into fixup_Mips_GOT. * MO_GOT16 and MO_GOT turned out to be identical and have been merged into MO_GOT. * VK_Mips_GOT and VK_Mips_GOT16 turned out to be the same thing so they have been merged into MEK_GOT Reviewers: sdardis Subscribers: dsanders, sdardis, llvm-commits Differential Revision: http://reviews.llvm.org/D19716 llvm-svn: 268379
* [mips][ias] Move createCpRestoreMemOp to MipsTargetStreamer. NFC.Daniel Sanders2016-04-291-4/+20
| | | | | | | | | | | | | | | Summary: This removes the temporary call to isIntegratedAssemblerRequired() which was added recently. It's effect is now acheived directly in the MipsTargetStreamer hierarchy. Reviewers: sdardis Subscribers: dsanders, sdardis, llvm-commits Differential Revision: http://reviews.llvm.org/D19715 llvm-svn: 268058
* [mips][ias] Split expandMemInst between MipsAsmParser and ↵Daniel Sanders2016-04-292-2/+2
| | | | | | | | | | | | | | | | | | | | | | MipsTargetStreamer. Almost NFC. Summary: The portion in MipsAsmParser is responsible for figuring out which expansion to use, while the portion in MipsTargetStreamer is responsible for emitting it. This allows us to remove the call to isIntegratedAssemblerRequired() which is currently ensuring the effect of .cprestore only occurs when writing objects. The small functional change is that the memory offsets are now correctly printed as signed values. Reviewers: sdardis Subscribers: dsanders, sdardis, llvm-commits Differential Revision: http://reviews.llvm.org/D19714 llvm-svn: 268042
* [mips][ias] Make section sizes a multiple of the alignment.Daniel Sanders2016-04-291-0/+106
| | | | | | | | | | Reviewers: sdardis Subscribers: dsanders, llvm-commits, sdardis Differential Revision: http://reviews.llvm.org/D19008 llvm-svn: 268036
* [mips][microMIPS] Fix offsets for LLE, LWE, SBE, SCE and SHE instructionsZlatko Buljan2016-04-296-7/+122
| | | | | | Differential Revision: http://reviews.llvm.org/D18645 llvm-svn: 268012
* [mips][microMIPS] Add CodeGen support for SUBU16, SUB, SUBU, DSUB and DSUBU ↵Zlatko Buljan2016-04-272-0/+10
| | | | | | | | instructions Differential Revision: http://reviews.llvm.org/D16676 llvm-svn: 267694
* [mips][microMIPS] Add CodeGen support for SLL16, SRL16, SLL, SLLV, SRA, ↵Zlatko Buljan2016-04-276-0/+84
| | | | | | | | SRAV, SRL and SRLV instructions Differential Revision: http://reviews.llvm.org/D17989 llvm-svn: 267693
* [mips][microMIPS] Revert commit r267137Hrvoje Varga2016-04-251-4/+0
| | | | | | Commit r267137 was the reason for failing tests in LLVM test suite. llvm-svn: 267419
* [mips][microMIPS] Revert commit r266977Zlatko Buljan2016-04-258-87/+0
| | | | | | Commit r266977 was reason for failing LLVM test suite with error message: fatal error: error in backend: Cannot select: t17: i32 = rotr t2, t11 ... llvm-svn: 267418
* [mips][microMIPS] Revert commit r266861.Zoran Jovanovic2016-04-225-20/+7
| | | | | | Commit r266861 was the reason for failing tests in LLVM test suite. llvm-svn: 267166
* [mips][microMIPS] Implement SLT, SLTI, SLTIU, SLTU microMIPS32r6 instructionsHrvoje Varga2016-04-221-0/+4
| | | | | | Differential Revision: http://reviews.llvm.org/D19354 llvm-svn: 267137
* [mips][microMIPS] Add R_MICROMIPS_PC18_S3 relocationZoran Jovanovic2016-04-222-0/+9
| | | | | | Differential Revision: http://reviews.llvm.org/D15026 llvm-svn: 267130
* [mips][microMIPS] Implement DVP, EVP and JALRC.HB instructionsZlatko Buljan2016-04-224-0/+24
| | | | | | Differential Revision: http://reviews.llvm.org/D18687 llvm-svn: 267114
* [mips][microMIPS] Implement ldpc instructionZoran Jovanovic2016-04-211-0/+1
| | | | | | Differential Revision: http://reviews.llvm.org/D15009 llvm-svn: 266990
* [mips][microMIPS] Add R_MICROMIPS_PC19_S2 relocationZoran Jovanovic2016-04-212-1/+16
| | | | | | Differential Revision: http://reviews.llvm.org/D14915 llvm-svn: 266988
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