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* [mips] Correct c.cond.fmt instruction definition.Simon Dardis2017-01-1634-390/+643
| | | | | | | | | | | | | | | Permit explicit $fcc<X> operand in c.cond.fmt instruction. Add c.cond.fmt to the MIPS to microMIPS instruction mapping table. Check that $fcc1 - $fcc7 are unusable for MIPS-I to MIPS-III for c.cond.fmt, bc1t, bc1f. Reviewers: seanbruno, zoran.jovanovic, vkalintiris Differential Revision: https://reviews.llvm.org/D24510 llvm-svn: 292117
* [mips] For PIC code convert unconditional jump to unconditional branchSimon Atanasyan2016-12-122-70/+207
| | | | | | | | | | | | Unconditional branch uses relative addressing which is the right choice in case of position independent code. This is a fix for the bug: https://dmz-portal.mips.com/bugz/show_bug.cgi?id=2445 Differential revision: https://reviews.llvm.org/D27483 llvm-svn: 289448
* [mips] Make the test case more specific and provide OS component of a ↵Simon Atanasyan2016-12-081-3/+3
| | | | | | triple. NFC llvm-svn: 289117
* [mips] Change instruction s/daddiu/addiu/ since O32 prohibits the use of ↵Simon Atanasyan2016-12-081-34/+34
| | | | | | 64-bit GPRs. NFC llvm-svn: 289115
* [mips][ias] N32/N64 must not sort the relocation table.Simon Dardis2016-12-051-2/+10
| | | | | | | | | | | | Doing so changes the evaluation order for relocation composition. Patch By: Daniel Sanders Reviewers: vkalintiris, atanasyan Differential Revision: https://reviews.llvm.org/D26401 llvm-svn: 288666
* [mips] Correct jal expansion for local symbols in .local directives.Simon Dardis2016-11-251-28/+127
| | | | | | | | | | | | | | | | | This patch corrects the behaviour of code such as: .local foo jal foo foo: to use the correct jal expansion when writing ELF files. Patch by: Daniel Sanders Reviewers: zoran.jovanovic, seanbruno, vkalintiris Differential Revision: https://reviews.llvm.org/D24722 llvm-svn: 287918
* [mips] seb, seh instruction aliasesSimon Dardis2016-11-2211-12/+40
| | | | | | | | | | Add the single operand form. Reviewers: vkalintiris Differential Revision: https://reviews.llvm.org/D26961 llvm-svn: 287681
* [mips] Add support for unaligned load/store macros.Vasileios Kalintiris2016-11-221-12/+652
| | | | | | | | Add missing unaligned store macros (ush/usw) and fix the exisiting implementation of the unaligned load macros in order to generate identical expansions with the GNU assembler. llvm-svn: 287646
* [mips] seq macro supportSimon Dardis2016-11-211-0/+52
| | | | | | | | | | | | | | This patch adds the seq macro. This partially resolves PR/30381. Thanks to Sean Bruno for reporting the issue! Reviewers: zoran.jovanovic, vkalintiris, seanbruno Differential Revision: https://reviews.llvm.org/D24607 llvm-svn: 287573
* [mips] not instruction aliasSimon Dardis2016-11-1618-0/+33
| | | | | | | | | | | This patch adds the single operand form of the not alias to microMIPS and MIPS along with additional tests. This partially resolves PR/30381. Thanks to Sean Bruno for reporting the issue! llvm-svn: 287097
* [mips] synci microMIPS instruction definition.Simon Dardis2016-10-241-0/+4
| | | | | | | | | | | | | Add synci to the microMIPS instruction definitions, mark the MIPS sync & synci as not being part of microMIPS. This does not cover the sync instruction alias, as that will be handled with a different patch. Add sync to the valid tests for microMIPS. Reviewers: vkalintiris Differential Revision: https://reviews.llvm.org/D25795 llvm-svn: 284962
* llvm/test/MC/Mips/macro-ld-sd.s: Sweep a spurious character \xA0 in the test ↵NAKAMURA Takumi2016-10-191-1/+1
| | | | | | | | file. It might crash FileCheck. llvm-svn: 284587
* [mips][ias] Handle more complicated expressions for memory operandsSimon Dardis2016-10-181-0/+33
| | | | | | | | | | | | | | | | This patch teaches ias for mips to handle expressions such as (8*4)+(8*31)($sp). Such expression typically occur from the expansion of multiple macro definitions. This partially resolves PR/30383. Thanks to Sean Bruno for reporting the issue! Reviewers: zoran.jovanovic, vkalintiris Differential Revision: https://reviews.llvm.org/D24667 llvm-svn: 284485
* [mips] Fix sync instruction definitionSimon Dardis2016-10-188-8/+8
| | | | | | | | | | | | | | | | | | | | | | | The 'sync' instruction for MIPS was defined in MIPS-II as taking no operands. MIPS32 extended the define of 'sync' as taking an optional unsigned 5 bit immediate. This patch correct the definition of sync so that it is accepted with an operand of 0 or no operand for MIPS-II to MIPS-V, and a 5 bit unsigned immediate for MIPS32 and later revisions. Additionally a clear error is given when the MIPS32 version of sync is used when targeting pre MIPS32. This partially resolves PR/30714. Thanks to Daniel Sanders for reporting this issue! Reveiwers: vkalintiris Differential Revision: https://reviews.llvm.org/D25672 llvm-svn: 284483
* [mips] Macro expansion for ld, sd for O32Simon Dardis2016-10-185-8/+24
| | | | | | | | | | | | | | | | | | | | | | ld and sd when assembled for the O32 ABI expand to a pair of 32 bit word loads or stores using the specified source or destination register and the next register. This patch does not add support for the cases where the offset is greater than a 16 bit signed immediate as that would lead to a wrong/misleading error message as the assembler would report "instruction requires a CPU feature not currently enabled" for ld & sd for MIPS64 when their offset is not a signed 16 bit number. This fixes PR/29159. Thanks to Sean Bruno for reporting this issue! Reviewers: vkalintiris, seanbruno, zoran.jovanovic Differential Review: https://reviews.llvm.org/D24556 llvm-svn: 284481
* [mips] Fix aui/daui/dahi/dati for MIPSR6Simon Dardis2016-10-147-13/+40
| | | | | | | | | | | | For compatiblity with binutils, define these instructions to take two registers with a 16bit unsigned immediate. Both of the registers have to be same for dahi and dati. Reviewers: dsanders, zoran.jovanovic Differential Review: https://reviews.llvm.org/D21473 llvm-svn: 284218
* [mips] Add IAS support for dvp, evpSimon Dardis2016-10-134-0/+20
| | | | | | | | | | | | | These instructions were only defined for microMIPSR6 previously. Add definitions for MIPSR6, correct definitions for microMIPSR6, flag these instructions as having unmodelled side effects (they disable/enable virtual processors) and add missing disassember tests for microMIPSR6. Reviewers: vkalintiris Differential Review: https://reviews.llvm.org/D24291 llvm-svn: 284115
* [MC] Fix Error Location for ParseIdentifierNirav Dave2016-10-121-1/+1
| | | | | | | Prevent partial parsing of '$' or '@' of invalid identifiers and fixup workaround points. NFC Intended. llvm-svn: 284017
* [mips][ias] fix li macro when values are negated with ~Simon Dardis2016-10-052-2/+10
| | | | | | | | | | | | | | | The integrated assembler evaluates the expressions such as ~0x80000000 to 0xffffffff7fffffff early in the parsing process. This patch adds compatibility with gas so that li loads the expected value (0x7fffffff) in those cases. This only occurs iff all the upper 32bits are set and maintains existing checks by not truncating the result down to 32 bits if any of the the upper bits are not set. Reviewers: dsanders, zoran.jovanovic Differential Review: https://reviews.llvm.org/D23399 llvm-svn: 283353
* Recommit: "[mips] Add rsqrt, recip for MIPS"Simon Dardis2016-10-0521-36/+48
| | | | | | | | | | | Add rsqrt.[ds], recip.[ds] for MIPS. Correct the microMIPS definitions for architecture support and register usage. Reviewers: vkalintiris, zoran.jovanoic Differential Review: https://reviews.llvm.org/D24499 llvm-svn: 283334
* Revert "[mips] Add rsqrt, recip for MIPS"Simon Dardis2016-10-0523-58/+38
| | | | | | | This reverts commit r282485 which contain two patches instead of one. llvm-svn: 283327
* [mips] Add rsqrt, recip for MIPSSimon Dardis2016-09-2723-38/+58
| | | | | | | | | | | Add rsqrt.[ds], recip.[ds] for MIPS. Correct the microMIPS definitions for architecture support and register usage. Reviewers: vkalintiris, zoran.jovanoic Differential Review: https://reviews.llvm.org/D24499 llvm-svn: 282485
* Revert "[mips] Fix aui/daui/dahi/dati for MIPSR6"Simon Dardis2016-09-167-40/+13
| | | | | | This reverts r281724. Still need dsanders to accept this. llvm-svn: 281726
* [mips] Fix aui/daui/dahi/dati for MIPSR6Simon Dardis2016-09-167-13/+40
| | | | | | | | | | | | For compatiblity with binutils, define these instructions to take two registers with a 16bit unsigned immediate. Both of the registers have to be same for dahi and dati. Reviewers: vkalintiris, dsanders, zoran.jovanovic Differential Review: https://reviews.llvm.org/D21473 llvm-svn: 281724
* Revert "[mips] Fix c.<cc>.<fmt> instruction definition."Simon Dardis2016-09-0920-352/+320
| | | | | | | This reverts commit r281022. Mips buildbot broke, due to unhandled register class FCC. llvm-svn: 281033
* [mips] Fix c.<cc>.<fmt> instruction definition.Simon Dardis2016-09-0920-320/+352
| | | | | | | | | | | | | | | As part of this effort, remove MipsFCmp nodes and use tablegen patterns rather than custom lowering through C++. Unexpectedly, this improves codesize for microMIPS as previous floating point setcc expansions would materialize 0 and 1 into GPRs before using the relevant mov[tf].[sd] instruction. Now $zero is used directly. Reviewers: dsanders, vkalintiris, zoran.jovanovic Differential Review: https://reviews.llvm.org/D23118 llvm-svn: 281022
* [mips][microMIPS] Implement DBITSWAP, DLSA and LWUPC and add tests for AUI ↵Hrvoje Varga2016-09-082-0/+16
| | | | | | | | instructions Differential Revision: https://reviews.llvm.org/D16452 llvm-svn: 280909
* [mips][ias] Support .dtprel[d]word and .tprel[d]word directivesSimon Atanasyan2016-08-221-6/+12
| | | | | | | | | | | | | Assembler directives .dtprelword, .dtpreldword, .tprelword, and .tpreldword generates relocations R_MIPS_TLS_DTPREL32, R_MIPS_TLS_DTPREL64, R_MIPS_TLS_TPREL32, and R_MIPS_TLS_TPREL64 respectively. The main motivation for this patch is to be able to write test cases for checking correctness of the LLD linker's behaviour. Differential Revision: https://reviews.llvm.org/D23669 llvm-svn: 279439
* [mips][microMIPS] Implement BLTZC, BLEZC, BGEZC and BGTZC instructions, fix ↵Hrvoje Varga2016-08-227-9/+245
| | | | | | | | disassembly and add operand checking to existing B<cond>C implementations Differential Revision: https://reviews.llvm.org/D22667 llvm-svn: 279429
* [mips] Add l.[sd] and s.[sd] instruction aliasesSimon Dardis2016-08-1714-0/+56
| | | | | | | | Reviewers: dsanders, vkalintiris Differential Review: https://reviews.llvm.org/D23121 llvm-svn: 278930
* Re-commit r277988: [mips][ias] Fix all the hacks related to MIPS-specific ↵Daniel Sanders2016-08-082-17/+26
| | | | | | | | | unary operators (%hi/%lo/%gp_rel/etc.). Hopefully with the MSVC builds fixed. I've added a missing '#include <tuple>' that gcc and clang don't seem to need. llvm-svn: 277995
* Revert r277988: [mips][ias] Fix all the hacks related to MIPS-specific unary ↵Daniel Sanders2016-08-082-26/+17
| | | | | | | | operators (%hi/%lo/%gp_rel/etc.). It seems that MSVC doesn't like std::tie(). llvm-svn: 277990
* [mips][ias] Fix all the hacks related to MIPS-specific unary operators ↵Daniel Sanders2016-08-082-17/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | (%hi/%lo/%gp_rel/etc.). Summary: They are now lexed as a single token on targets where MCAsmInfo::HasMipsExpressions is true and then parsed in a similar way to the '~' operator as part of MCExpr::parseExpression. As a result: * expressions and immediates no longer have different parsing rules. The difference is now solely down to whether evaluateAsAbsolute() succeeds. * %hi(%neg(%gp_rel(x))) are no longer parsed as a single operator and decomposed into the three MipsMCExpr nodes. They are parsed directly as three MipsMCExpr nodes. * parseMemOperand no longer needs to eat all the surrounding parenthesis to get at the outermost operator to make this work * %hi(%neg(%gp_rel(x))) and %lo(%neg(%gp_rel(x))) are no longer the only 3-in-1 relocs that parse for N64. They're still the only combinations that are permitted in relocatable expressions though. Fixing that should be a later patch. * We no longer need to list all the tokens that can occur as the first token of an expression or immediate. test/MC/Mips/expr1.s: This change also prevents the incorrect lowering of %lo(2*4)+foo to %lo(8+foo) which is not an equivalent expression (the difference is whether foo is truncated to 16-bit or not) and the test has been updated to account for the macro expansion the correct expression requires. Reviewers: sdardis Subscribers: dsanders, sdardis, llvm-commits Differential Revision: https://reviews.llvm.org/D23110 llvm-svn: 277988
* [mips][microMIPS] Implement CFC1, CFC2, CTC1 and CTC2 instructionsHrvoje Varga2016-08-043-0/+213
| | | | | | Differential Revision: https://reviews.llvm.org/D22347 llvm-svn: 277719
* [mips][ias] Check '$rs = $rd' constraints when both registers are in AsmText.Daniel Sanders2016-07-272-6/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This is one possible solution to the problem of ignoring constraints that Simon raised in D21473 but it's a bit of a hack. The integrated assembler currently ignores violations of the tied register constraints when the operands involved in a tie are both present in the AsmText. For example, 'dati $rs, $rt, $imm' with the '$rs = $rt' will silently replace $rt with $rs. So 'dati $2, $3, 1' is processed as if the user provided 'dati $2, $2, 1' without any diagnostic being emitted. This is difficult to solve properly because there are multiple parts of the matcher that are silently forcing these constraints to be met. Tied operands are rendered to instructions by cloning previously rendered operands but this is unnecessary because the matcher was already instructed to render the operand it would have cloned. This is also unnecessary because earlier code has already replaced the MCParsedOperand with the one it was tied to (so the parsed input is matched as if it were 'dati <RegIdx 2>, <RegIdx 2>, <Imm 1>'). As a result, it looks like fixing this properly amounts to a rewrite of the tied operand handling which affects all targets. This patch however, merely inserts a checking hook just before the substitution of MCParsedOperands and the Mips target overrides it. It's not possible to accurately check the registers are the same this early (because numeric registers haven't been bound to a register class yet) so it cheats a bit and checks that the tokens that produced the operand are lexically identical. This works because tied registers need to have the same register class but it does have a flaw. It will reject 'dati $4, $a0, 1' for violating the constraint even though $a0 ends up as the same register as $4. Reviewers: sdardis Subscribers: dsanders, llvm-commits, sdardis Differential Revision: https://reviews.llvm.org/D21994 llvm-svn: 276867
* [mips] sgtu, s[rl]l, sra, dnegu, neg instruction aliasesSimon Dardis2016-07-2617-0/+142
| | | | | | | | | | | Add the instruction alias sgtu (register form only), two operand forms of s[rl]l and sra, and missing single/two operand forms of dnegu/neg. Reviewers: dsanders Differential Revision: https://reviews.llvm.org/D22752 llvm-svn: 276736
* [mips][microMIPS] Implement SLT, SLTI, SLTIU, SLTU microMIPS32r6 instructionsHrvoje Varga2016-07-222-1/+5
| | | | | | Differential Revision: https://reviews.llvm.org/D19906 llvm-svn: 276397
* [mips][ias] R_MIPS_GOT_(PAGE|OFST) do not need symbolsDaniel Sanders2016-07-191-5/+31
| | | | | | | | | | Reviewers: sdardis Subscribers: dsanders, llvm-commits, sdardis Differential Revision: https://reviews.llvm.org/D22458 llvm-svn: 275968
* [mips] Correct label prefixes for N32 and N64.Daniel Sanders2016-07-1910-36/+42
| | | | | | | | | | | | | | | | | Summary: N32 and N64 follow the standard ELF conventions (.L) whereas O32 uses its own ($). This fixes the majority of object differences between -fintegrated-as and -fno-integrated-as. Reviewers: sdardis Subscribers: dsanders, sdardis, llvm-commits Differential Revision: https://reviews.llvm.org/D22412 llvm-svn: 275967
* [mips][microMIPS] Implement LDC1, SDC1, LDC2, SDC2, LWC1, SWC1, LWC2 and ↵Zlatko Buljan2016-07-1117-10/+296
| | | | | | | | SWC2 instructions and add CodeGen support Differential Revision: http://reviews.llvm.org/D18824 llvm-svn: 275050
* [mips][micromips] Implement LD, LLD, LWU, SD, DSRL, DSRL32 and DSRLV ↵Hrvoje Varga2016-06-2715-15/+55
| | | | | | | | instructions Differential Revision: http://reviews.llvm.org/D16625 llvm-svn: 273850
* [mips] Use --check-prefixes where appropriate. NFC.Daniel Sanders2016-06-2411-40/+36
| | | | llvm-svn: 273669
* [mips] Don't derive the default ABI from the CPU in the backend.Daniel Sanders2016-06-2311-25/+25
| | | | | | | | | | | | | | | | | | | | | | | | Summary: The backend has no reason to behave like a driver and should generally do as it's told (and error out if it can't) instead of trying to figure out what the API user meant. The default ABI is still derived from the arch component as a concession to backwards compatibility. API-users that previously passed an explicit CPU and a triple that was inconsistent with the CPU (e.g. mips-linux-gnu and mips64r2) may get a different ABI to what they got before. However, it's expected that there are no such users on the basis that CodeGen has been asserting that the triple is consistent with the selected ABI for several releases. API-users that were consistent or passed '' or 'generic' as the CPU will see no difference. Reviewers: sdardis, rafael Subscribers: rafael, dsanders, sdardis, llvm-commits Differential Revision: http://reviews.llvm.org/D21466 llvm-svn: 273557
* [mips][ias] Integers are not registers.Daniel Sanders2016-06-231-0/+30
| | | | | | | | | | | | | | | | | | | Summary: When parseAnyRegister() encounters a symbol alias, it parses integers and adds a corresponding expression to the operand list. This is clearly wrong since the only operands that parseAnyRegister() should be accepting are registers. It's not clear why this code was added and there are no test cases that cover it. I think it might be leftover from when searchSymbolAlias() was more widely used. Reviewers: sdardis Subscribers: dsanders, sdardis, llvm-commits Differential Revision: http://reviews.llvm.org/D21377 llvm-svn: 273555
* [mips] Fix dext/dins definitionsSimon Dardis2016-06-231-0/+6
| | | | | | | | | | | dext and dins, along with their 'm' and 'u' variants are defined in mips64r2, not mips64. Reviewers: dsanders, vkalintiris Differential Review: http://reviews.llvm.org/D21608 llvm-svn: 273549
* [llvm-objdump] Support detection of feature bits from the object and ↵Daniel Sanders2016-06-1610-85/+29
| | | | | | | | | | | | | | | | | | | | implement this for Mips. Summary: The Mips implementation only covers the feature bits described by the ELF e_flags so far. Mips stores additional feature bits such as MSA in the .MIPS.abiflags section. Also fixed a small bug this revealed where microMIPS wouldn't add the EF_MIPS_MICROMIPS flag when using -filetype=obj. Reviewers: echristo, rafael Subscribers: rafael, mehdi_amini, dsanders, sdardis, llvm-commits Differential Revision: http://reviews.llvm.org/D21125 llvm-svn: 272880
* [mips][micromips] Implement DCLO, DCLZ, DROTR, DROTR32 and DROTRV instructionsHrvoje Varga2016-06-162-0/+9
| | | | | | Differential Revision: http://reviews.llvm.org/D16917 llvm-svn: 272876
* [mips][microMIPS] Add CodeGen support for AND*, OR16, OR*, XOR*, NOT16 and ↵Zlatko Buljan2016-06-156-0/+81
| | | | | | | | NOR instructions Differential Revision: http://reviews.llvm.org/D16719 llvm-svn: 272764
* [mips][ias] Implement one N32 case (of two) for .cpsetup.Daniel Sanders2016-06-141-28/+16
| | | | | | | | | | | | | | | | | | | | | | This patch implements the N32 case where -mno-shared is in effect. The case where -mshared is in effect will be added later since doing that now requires additional changes to how we handle %hi(%neg(%gp_rel(foo))) expressions to emit the three relocations as three relocations (currently only one of the three would be emitted) which then requires further changes to our MCFixup handling. While we could fix both cases together, fixing the -mno-shared case allows us to fix the ELFCLASS bug (where N32 incorrectly uses ELFCLASS64 instead of ELFCLASS32) in a way that allows cpsetup.s to check for a correct output instead of another incorrect output. Reviewers: sdardis Subscribers: dsanders, llvm-commits, sdardis Differential Revision: http://reviews.llvm.org/D21131 llvm-svn: 272652
* [mips][microMIPS] Implement BOVC, BNVC, EXT, INS and JALRC instructionsHrvoje Varga2016-06-092-0/+10
| | | | | | Differential Revision: http://reviews.llvm.org/D11798 llvm-svn: 272259
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