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* [mips] Move conditional moves out of isCodeGenOnlySimon Dardis2018-05-091-0/+16
| | | | | | | | Reviewers: atanasyan, smaksimovic, abeserminji Differential Revision: https://reviews.llvm.org/D46389 llvm-svn: 331863
* [mips] Mark various memory instructions as being in microMIPS (NFC)Simon Dardis2018-05-081-2/+44
| | | | | | | | Reviewers: atanasyan, abeserminji, smaksimovic Differential Revision: https://reviews.llvm.org/D46388 llvm-svn: 331756
* [mips] Correct clo/clz predicatesSimon Dardis2018-05-086-0/+12
| | | | | | | | Reviewers: smaksimovic, abeserminji, atanasyan Differential Revision: https://reviews.llvm.org/D46125 llvm-svn: 331754
* [mips] Correct the predicates of sign extension instructionsSimon Dardis2018-05-049-4/+40
| | | | | | | | | | And eliminatw the duplication of those instructions for microMIPS32r6. Reviewers: smaksimovic, abeserminji, atanasyan Differential Revision: https://reviews.llvm.org/D46117 llvm-svn: 331526
* Revert "[mips] Correct the predicates of sign extension instructions"Simon Dardis2018-05-029-40/+4
| | | | | | | | | I accidently committed this patch after asking for a review, but it has not been reviewed yet. This reverts r331346. llvm-svn: 331348
* [mips] Correct the predicates of sign extension instructionsSimon Dardis2018-05-029-4/+40
| | | | | | And eliminate the duplication of those instructions for microMIPS32r6. llvm-svn: 331346
* [mips] Correct the predicates for shifts.Simon Dardis2018-05-0216-11/+495
| | | | | | | | Reviewers: smaksimovic, abeserminji, atanasyan Differential Revision: https://reviews.llvm.org/D46123 llvm-svn: 331341
* [mips] Fix microMIPS loads and stores.Simon Dardis2018-04-302-8/+8
| | | | | | | | | | | Previously these instructions were unselectable and instead were generated through the instruction mapping tables. Reviewers: atanasyan, smaksimovic, abeserminji Differential Revision: https://reviews.llvm.org/D46055 llvm-svn: 331165
* [mips] Add support for Virtualization ASEPetar Jovanovic2018-04-279-0/+232
| | | | | | | | | | | | | | | | | | | This includes Instructions: tlbginv, tlbginvf, tlbgp, tlbgr, tlbgwi, tlbgwr, hypcall mfgc0, mtgc0, mfhgc0, mthgc0, dmfgc0, dmtgc0, Assembler directives: .set virt, .set novirt, .module virt, .module novirt Attribute: virt .MIPS.abiflags: VZ (0x100) Patch by Vladimir Stefanovic. Differential Revision: https://reviews.llvm.org/D44905 llvm-svn: 331024
* [mips] Accept 32-bit offsets for lb and lbu commandsSimon Atanasyan2018-04-267-24/+42
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | `lb` and `lbu` commands accepts 16-bit signed offsets. But GAS accepts larger offsets for these commands. If an offset does not fit in 16-bit range, `lb` command is translated into lui/lb or lui/addu/lb series. It's interesting that initially LLVM assembler supported this feature, but later it was broken. This patch restores support for 32-bit offsets. It replaces `mem_simm16` operand for `LB` and `LBu` definitions by the new `mem_simmptr` operand. This operand is intended to check that offset fits to the same size as using for pointers. Later we will be able to extend this rule and accepts 64-bit offsets when it is possible. Some issues remain: - The regression also affects LD, SD, LH, LHU commands. I'm going to fix them by a separate patch. - GAS accepts any 32-bit values as an offset. Now LLVM accepts signed 16-bit values and this patch extends the range to signed 32-bit offsets. In other words, the following code accepted by GAS and still triggers an error by LLVM: ``` lb $4, 0x80000004 # gas lui a0, 0x8000 lb a0, 4(a0) ``` - In case of 64-bit pointers GAS accepts a 64-bit offset and translates it to the li/dsll/lb series of commands. LLVM still rejects it. Probably this feature has never been implemented in LLVM. This issue is for a separate patch. ``` lb $4, 0x800000001 # gas li a0, 0x8000 dsll a0, a0, 0x14 lb a0, 4(a0) ``` Differential Revision: https://reviews.llvm.org/D45020 llvm-svn: 330983
* [mips] Fix a test case which is keeping the expensive checks bot win red (NFC)Simon Dardis2018-04-261-3/+0
| | | | llvm-svn: 330956
* [mips] Correct the definitions of some control instructionsSimon Dardis2018-04-262-10/+29
| | | | | | | | | | | | | | Correct the definitions of ei, di, eret, deret, wait, syscall and break. Also provide microMIPS specific aliases to match the MIPS aliases. Additionally correct the definition of the wait instruction so that it is present in the instruction mapping tables. Reviewers: smaksimovic, abeserminji, atanasyan Differential Revision: https://reviews.llvm.org/D45939 llvm-svn: 330952
* [mips] Fix the definition of sync, synciSimon Dardis2018-04-259-7/+40
| | | | | | | | | | Also, fix the disassembly of synci for microMIPS. Reviewers: abeserminji, smaksimovic, atanasyan Differential Revision: https://reviews.llvm.org/D45870 llvm-svn: 330810
* Reland "[mips] Guard traps for microMIPS correctly"Simon Dardis2018-04-2412-216/+216
| | | | | | | | | | | | | | This is part of fixing the instruction predicates for MIPS. Reviewers: atanasyan, abeserminji Differential Revision: https://reviews.llvm.org/D44212 This patch relands r327409, hopefully without the problematic part of the tests that cause FileCheck to assert on the windows expensive checks bot. llvm-svn: 330741
* [mips] Show an error if register number is out of rangeSimon Atanasyan2018-04-2412-194/+191
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Current code does not check that a register number is in the 0-31 range. Sometimes the parser checks that later for some kinds of instructions, but that leads to unclear / incorrect error messages like that: % cat test.s .text lb $4, 8($32) % llvm-mc test.s -triple=mips64-unknown-linux test.s:2:10: error: expected memory with 16-bit signed offset lb $4, 8($32) ^ Sometimes the parser just crashes: % cat test.s .text lw $4, 8($32) % llvm-mc test.s -triple=mips64-unknown-linux This patch resolves the problem by checking that register number after '$' sign is in the 0-31 range. If the number is out of the range the parser shows the `invalid register number` error, but treats invalid register number as a normal one to continue parsing and catch other possible errors. Differential Revision: https://reviews.llvm.org/D45919 llvm-svn: 330732
* [mips] Guard some macro expansions properlySimon Dardis2018-04-191-216/+663
| | | | | | | | Reviewers: atanasyan, abeserminji Differential Revision: https://reviews.llvm.org/D45565 llvm-svn: 330315
* [mips] Restrict certain trap instructions for micromipsr6Stefan Maksimovic2018-04-161-0/+6
| | | | | | | | | Instructions removed from micromipsr6: teqi, tgei, tgeiu, tlti, tltiu, tnei Differential Revision: https://reviews.llvm.org/D45318 llvm-svn: 330114
* [mips] Correct the predicates of the load/store (double)word for coprocessor 3.Simon Dardis2018-04-123-0/+12
| | | | llvm-svn: 329913
* [mips] Correct the predicates for special nops, tlb ctrl instrs, software ↵Simon Dardis2018-04-1215-8/+194
| | | | | | | | | | breakpoint and prefx. Reviewers: atanasyan, abeserminji Differential Revision: https://reviews.llvm.org/D44436 llvm-svn: 329905
* Use .set instead of = when printing assignment in assembly outputKrzysztof Parzyszek2018-03-271-1/+1
| | | | | | | | | On Hexagon "x = y" is a syntax used in most instructions, and is not treated as a directive. Differential Revision: https://reviews.llvm.org/D44256 llvm-svn: 328635
* [mips] Add support for CRC ASEPetar Jovanovic2018-03-148-0/+166
| | | | | | | | | | | | | | | | | | | This includes Instructions: crc32b, crc32h, crc32w, crc32d, crc32cb, crc32ch, crc32cw, crc32cd Assembler directives: .set crc, .set nocrc, .module crc, .module nocrc Attribute: crc .MIPS.abiflags: CRC (0x8000) Patch by Vladimir Stefanovic. Differential Revision: https://reviews.llvm.org/D44176 llvm-svn: 327511
* Revert "[mips] Guard traps for microMIPS correctly"Simon Dardis2018-03-1315-574/+82
| | | | | | | | | This appears to have broken the expensive checks bot in a strange fashion. Reverting until I can investigate. This reverts r327409. llvm-svn: 327427
* [mips] Guard traps for microMIPS correctlySimon Dardis2018-03-1315-82/+574
| | | | | | | | | | This is part of fixing the instruction predicates for MIPS. Reviewers: atanasyan, abeserminji Differential Revision: https://reviews.llvm.org/D44212 llvm-svn: 327409
* [mips] Fix the definitions of the EVA instructionsSimon Dardis2018-03-138-63/+177
| | | | | | | | | | Correct their availability to their respective ISAs. Reviewers: atanasyan Differential Revision: https://reviews.llvm.org/D44209 llvm-svn: 327403
* [mips] Correct the definition of m(f|t)c(0|2)Simon Dardis2018-03-0710-12/+34
| | | | | | | | | | | | | | | | | | | | | | | | | These instructions are defined as taking a GPR register and a coprocessor register for ISAs up to MIPS32. MIPS32 extended the definition to allow a selector--a value from 0 to 32--to access another register. These instructions are now internally defined as being MIPS-I instructions, but are rejected for pre-MIPS32 ISA's if they have an explicit selector which is non-zero. This deviates slightly from GAS's behaviour which rejects assembly instructions with an explicit selector for pre-MIPS32 ISAs. E.g: mfc0 $4, $5, 0 is rejected by GAS for MIPS-I to MIPS-V but will be accepted with this patch for MIPS-I to MIPS-V. Reviewers: atanasyan Differential Revision: https://reviews.llvm.org/D41662 llvm-svn: 326890
* [mips] Correct the definition of cvt.d.wSimon Dardis2018-02-202-4/+8
| | | | | | | | An upcoming patch D41434, changes the ordering of the matcher table for assembly. This patch corrects the definition of the normal MIPS cvt.d.w not to be available in microMIPS. llvm-svn: 325589
* Make test changes added in r324584 more robust by using a regex instead of ↵Douglas Yung2018-02-096-66/+66
| | | | | | hard coded MCInst numbers. llvm-svn: 324699
* [mips] Define certain instructions in microMIPS32r3Stefan Maksimovic2018-02-0812-99/+297
| | | | | | | | | | | | | | | | | | | | Instructions affected: mthc1, mfhc1, add.d, sub.d, mul.d, div.d, mov.d, neg.d, cvt.w.d, cvt.d.s, cvt.d.w, cvt.s.d These instructions are now defined for microMIPS32r3 + microMIPS32r6 in MicroMipsInstrFPU.td since they shared their encoding with those already defined in microMIPS32r6InstrInfo.td and have been therefore removed from the latter file. Some instructions present in MicroMipsInstrFPU.td which did not have both AFGR64 and FGR64 variants defined have been altered to do so. Differential revision: https://reviews.llvm.org/D42738 llvm-svn: 324584
* [mips] Properly select abs and sqrt instructionsStefan Maksimovic2018-01-2312-33/+107
| | | | | | | | | | | | | - Alter abs for micromips to have both AFGR64 and FGR64 variants, same as sqrt - Remove sqrt and abs from MicroMips32r6InstrInfo.td, use micromips FGR64 variants - Restrict non-micromips abs/sqrt with NotInMicroMips predicate Differential revision: https://reviews.llvm.org/D41439 llvm-svn: 323184
* [Mips] Handle one byte unsupported relocationsStefan Maksimovic2018-01-111-0/+13
| | | | | | | | | Fail gracefully instead of crashing upon encountering this type of relocation. Differential revision: https://reviews.llvm.org/D41857 llvm-svn: 322266
* [mips] Fix the invalid EVA testSimon Dardis2017-12-211-23/+24
| | | | | | | | During the review of D40362 I spotted that this test wasn't actually testing the eva instructions due to '-mattr==eva', rather than '-mattr=+eva', which resulted in test having no effect. llvm-svn: 321273
* [AArch64][SVE] Re-submit patch series for ZIP1/ZIP2Sander de Smalen2017-12-2026-184/+184
| | | | | | | | | | | This patch resubmits the SVE ZIP1/ZIP2 patch series consisting of of r320992, r320986, r320973, and r320970 by reverting https://reviews.llvm.org/rL321024. The issue that caused r321024 has been addressed in https://reviews.llvm.org/rL321158, so this patch-series should be safe to resubmit. llvm-svn: 321163
* Revert "[AArch64][SVE] Asm" changes, they broke libjpeg_turboReid Kleckner2017-12-1826-184/+184
| | | | | | | | | | This reverts changes r320992, r320986, r320973, and r320970. r320970 by itself breaks the test case, and the rest depend on it. Test case will land soon. llvm-svn: 321024
* [TableGen][AsmMatcherEmitter] Only choose specific diagnostic for enabled ↵Sander de Smalen2017-12-1826-184/+184
| | | | | | | | | | | | | | | | | | | | | | | instruction Summary: When emitting a diagnostic for an invalid operand, a specific diagnostic should only be reported when the instruction being matched is actually enabled by the feature flags. Patch [3/4] in a series to add parsing of predicates and properly parse SVE ZIP1/ZIP2 instructions. This patch fixes bogus diagnostic messages for when the SVE feature is not specified. Reviewers: rengolin, craig.topper, olista01, sdardis, stoklund Reviewed By: olista01, sdardis Subscribers: fhahn, javed.absar, llvm-commits Differential Revision: https://reviews.llvm.org/D40362 llvm-svn: 320986
* [mips] Removal of microMIPS64R6Aleksandar Beserminji2017-12-116-869/+16
| | | | | | | | | | | All files and parts of files related to microMIPS4R6 are removed. When target is microMIPS4R6, errors are printed. This is LLVM part of patch. Differential Revision: https://reviews.llvm.org/D35625 llvm-svn: 320350
* [mips] Fix definition of 'bc' instructionSimon Dardis2017-12-062-2/+4
| | | | llvm-svn: 319888
* [CodeGen] Unify MBB reference format in both MIR and debug outputFrancis Visoiu Mistrih2017-12-0410-13/+13
| | | | | | | | | | | | | | | | As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
* [mips] Set microMIPS ASE flagAleksandar Beserminji2017-11-241-0/+10
| | | | | | | | | | This patch fixes an issue where microMIPS ASE flag is not set when a function has micromips attribute or when .set micromips directive is used. Differential Revision: https://reviews.llvm.org/D40316 llvm-svn: 318948
* [mips][mt] Add missing test cases from r318207Simon Dardis2017-11-165-0/+100
| | | | llvm-svn: 318389
* Reland "[mips][mt][6/7] Add support for mftr, mttr instructions."Simon Dardis2017-11-142-11/+32
| | | | | | | | | | | | | | | | | | | | This adjusts the tests to hopfully pacify the llvm-clang-x86_64-expensive-checks-win buildbot. Unlike many other instructions, these instructions have aliases which take coprocessor registers, gpr register, accumulator (and dsp accumulator) registers, floating point registers, floating point control registers and coprocessor 2 data and control operands. For the moment, these aliases are treated as pseudo instructions which are expanded into the underlying instruction. As a result, disassembling these instructions shows the underlying instruction and not the alias. Reviewers: slthakur, atanasyan Differential Revision: https://reviews.llvm.org/D35253 llvm-svn: 318207
* [mips] Correct microMIP's jump and add unconditional branch pseudoSimon Dardis2017-11-091-0/+17
| | | | | | | | | | | | | | Correct the definition of 'j' as being unavailable for microMIPS32R6 and provide the 'b' assembly idiom for codegen purposes for microMIPS32r3. Provide the necessary 'br' pattern for microMIPS32R6 as it now longer incorrectly uses the 'j' instruction. Reviewers: atanasyan Differential Revision: https://reviews.llvm.org/D39741 llvm-svn: 317801
* [mips] Add movep for microMIPS32R6 and fix microMIPS32r3 versionSimon Dardis2017-11-062-2/+2
| | | | | | | | | | | | | | | | | | | Previously, the 'movep' instruction was defined for microMIPS32r3 and shared that definition with microMIPS32R6. 'movep' was re-encoded for microMIPS32r6, so this patch provides the correct encoding. Secondly, correct the encoding of the 'rs' and 'rt' operands which have an instruction specific encoding for the registers those operands accept. Finally, correct the decoding of the 'dst_regs' operand which was extracting the relevant field from the instruction, but was actually extracting the field from the alreadly extracted field. Reviewers: atanasyan Differential Revision: https://reviews.llvm.org/D39495 llvm-svn: 317475
* [mips] Fix PR35140Simon Dardis2017-11-061-0/+28
| | | | | | | | | | | | | | Mark all symbols involved with TLS relocations as being TLS symbols. This resolves PR35140. Thanks to Alex Crichton for reporting the issue! Reviewers: atanasyan Differential Revision: https://reviews.llvm.org/D39591 llvm-svn: 317470
* [mips] Fix (dis)assembly of abs.fmt for micromipsSimon Dardis2017-10-261-0/+4
| | | | | | | | | | | These instructions were previously marked as codegen only preventing them from being assembled as microMIPS or disassembled. Reviewers: atanasyan, abeserminji Differential Revision: https://reviews.llvm.org/D39123 llvm-svn: 316656
* [mips][micromips] Fix (dis)assembly of bc1(t|f)Simon Dardis2017-10-161-3/+7
| | | | | | | | | | | | Previously these instructions were marked codegen only and had an under-specified instruction description that did not record the fcc register. Reviewers: atanasyan, abeserminji Differential Revision: https://reviews.llvm.org/D38847 llvm-svn: 315905
* [mips] Duplicate the reciprocal instruction definitions for FP32Simon Dardis2017-10-103-3/+3
| | | | | | | | | | | | | Add instruction definitions for FP32 mode for recip.d and rsqrt.d. Previously these instructions were only defined when targeting the full 64-bit FPU model but were not guarded properly. Reviewers: nitesh.jain, atanasyan Differential Revision: https://reviews.llvm.org/D38400 llvm-svn: 315318
* [mips] Partially fix PR34391Simon Dardis2017-10-102-0/+73
| | | | | | | | | | | | | | | | | | | | | | | | Previously, the parsing of the 'subu $reg, ($reg,) imm' relied on a parser which also rendered the operand to the instruction. In some cases the general parser could construct an MCExpr which was not a MCConstantExpr which MipsAsmParser was expecting. Address this by altering the special handling to cope with unexpected inputs and fine-tune the handling of cases where an register name that is not available in the current ABI is regarded as not a match for the custom parser but also not as an outright error. Also enforces the binutils restriction that only constants are accepted. This partially resolves PR34391. Thanks to Ed Maste for reporting the issue! Reviewers: nitesh.jain, arichardson Differential Revision: https://reviews.llvm.org/D37476 llvm-svn: 315310
* [mips] implement .set dspr2 directivePetar Jovanovic2017-10-053-1/+21
| | | | | | | | | | | | Implement .set dspr2 directive with appropriate feature bits. This directive is a counterpart of -mattr=dspr2 command line option with the exception that it does not influence elf header flags. Patch by Milos Stojanovic. Differential Revision: https://reviews.llvm.org/D38537 llvm-svn: 314994
* [mips] Add test cases for dext/dins family of instructionsAleksandar Beserminji2017-09-294-1/+41
| | | | | | | | | Add missing test cases for dext, dextm, dextu, dins, dinsm and dinsu instructions. Differential Revision: https://reviews.llvm.org/D37741 llvm-svn: 314503
* [mips] Remove codegen support for branch likely instructions.Simon Dardis2017-09-281-18/+17
| | | | | | | | | | | | | | | | | | This patch disables codegen support for branch likely instructions to address a potential bug. These branches were unselectable as they had the same patterns as the normal branches but came after them when ISel was concerned. The branch likely instructions were marked as having no delay slots when they have annulling delay slots. The delay slot filler does not currently handle annulling delay slot branches, so this would lead to wrong codegen if these branches were generated. Reviewers: atanasyan, nitesh.jain Differential Revision: https://reviews.llvm.org/D38169 llvm-svn: 314421
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