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* [mips] Use MipsMCExpr instead of MCSymbolRefExpr for all relocations.Daniel Sanders2016-05-031-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This is much closer to the way MIPS relocation expressions work (%hi(foo + 2) rather than %hi(foo) + 2) and removes the need for the various bodges in MipsAsmParser::evaluateRelocExpr(). Removing those bodges ensures that the constant stored in MCValue is the full 32 or 64-bit (depending on ABI) offset from the symbol. This will be used to correct the %hi/%lo matching needed to sort the relocation table correctly. As part of this: * Gave MCExpr::print() the ability to omit parenthesis when emitting a symbol reference inside a MipsMCExpr operator like %hi(X). Without this we print things like %lo(($L1)). * %hi(%neg(%gprel(X))) is now three MipsMCExpr's instead of one. Most of the related special cases have been removed or moved to MipsMCExpr. We can remove the rest as we gain support for the less common relocations when they are not part of this specific combination. * Renamed MipsMCExpr::VariantKind and the enum prefix ('VK_') to avoid confusion with MCSymbolRefExpr::VariantKind and its prefix (also 'VK_'). * fixup_Mips_GOT_Local and fixup_Mips_GOT_Global were found to be identical and merged into fixup_Mips_GOT. * MO_GOT16 and MO_GOT turned out to be identical and have been merged into MO_GOT. * VK_Mips_GOT and VK_Mips_GOT16 turned out to be the same thing so they have been merged into MEK_GOT Reviewers: sdardis Subscribers: dsanders, sdardis, llvm-commits Differential Revision: http://reviews.llvm.org/D19716 llvm-svn: 268379
* [mips][microMIPS] Revert commit r266861.Zoran Jovanovic2016-04-221-2/+1
| | | | | | Commit r266861 was the reason for failing tests in LLVM test suite. llvm-svn: 267166
* [mips][microMIPS]Implement CFC*, CTC* and LDC* instructionsHrvoje Varga2016-04-201-1/+2
| | | | | | Differential Revision: http://reviews.llvm.org/D18640 llvm-svn: 266861
* Summary:Simon Dardis2016-04-141-0/+2
| | | | | | | | | | Alias 'jic $reg, 0' to 'jrc $reg' and 'jialc $reg, 0' to 'jalrc $reg' like binutils. This patch was previous committed as r266055 as seemed to have caused some spurious test failures. They did not reappear after further local testing. llvm-svn: 266301
* Revert "[mips] MIPSR6 Compact branch aliases"Simon Dardis2016-04-121-2/+0
| | | | | | | | This reverts commit r266055. ps4-buildslave2 is highlighting a failure. llvm-svn: 266061
* [mips] MIPSR6 Compact branch aliasesSimon Dardis2016-04-121-0/+2
| | | | | | | | | | | | Summary: Alias 'jic $reg, 0' to 'jrc $reg' and 'jialc $reg, 0' to 'jalrc $reg' like binutils. Reviewers: dsanders Differential Revision: http://reviews.llvm.org/D18856 llvm-svn: 266055
* [MIPS][LLVM-MC] Fix JR encoding for MIPSR6 ISASagar Thakur2016-04-011-0/+2
| | | | | | | | | | Summary: The assembler was picking the wrong JR variant because the pre-R6 one was still enabled at R6. Author: nitesh.jain Reviewers: vkalintiris, dsanders Subscribers: dsanders, llvm-commits, mohit.bhakkad, sagar, bhushan, jaydeep Differential: D18387 llvm-svn: 265134
* [mips] Range check simm16Daniel Sanders2016-03-311-2/+2
| | | | | | | | | | | | | | | | | | | Summary: There are too many instructions to exhaustively test so addiu and lwc2 are used as representative examples. It should be noted that many memory instructions that should have simm16 range checking do not because it is also necessary to support the macro of the same name which accepts simm32. The range checks for these occur in the macro expansion. Reviewers: vkalintiris Subscribers: dsanders, llvm-commits Differential Revision: http://reviews.llvm.org/D18437 llvm-svn: 265019
* [mips] Range check simm9 and fix a bug this revealed.Daniel Sanders2016-03-312-8/+8
| | | | | | | | | | | | | | Summary: The bug was that microMIPS's [ls]w[lr]e instructions claimed to support a 12-bit offset when it is only 9-bit. Reviewers: vkalintiris Subscribers: llvm-commits, dsanders Differential Revision: http://reviews.llvm.org/D18434 llvm-svn: 265010
* [mips] Invalid tests for MTC0, MTC2, MFC0, MFC2, DMTC0, DMFC0 MIPS instructionsHrvoje Varga2016-03-111-0/+4
| | | | | | Differential Revision: http://reviews.llvm.org/D18037 llvm-svn: 263203
* [mips] Range check uimm20 and fixed a bug this revealed.Daniel Sanders2016-02-291-0/+2
| | | | | | | | | | | | | | | | | | | Summary: The bug was that dextu's operand 3 would print 0-31 instead of 32-63 when printing assembly. This came up when replacing MipsInstPrinter::printUnsignedImm() with a version that could handle arbitrary bit widths. MipsAsmPrinter::printUnsignedImm*() don't seem to be used so they have been removed. Reviewers: vkalintiris Subscribers: dsanders, llvm-commits Differential Revision: http://reviews.llvm.org/D15521 llvm-svn: 262231
* [mips] Never select JAL for calls to an absolute immediate address.Daniel Sanders2016-01-111-0/+1
| | | | | | | | | | | | | | | Summary: It actually takes an offset into the current PC-region. This fixes the 'expr' command in lldb. Reviewers: vkalintiris, jaydeep, bhushan Subscribers: dsanders, llvm-commits Differential Revision: http://reviews.llvm.org/D16054 llvm-svn: 257339
* [mips][microMIPS][DSP] Implement PACKRL.PH, PICK.PH, PICK.QB, SHILO, SHILOV ↵Zlatko Buljan2015-12-181-0/+1
| | | | | | | | and WRDSP instructions Differential Revision: http://reviews.llvm.org/D14429 llvm-svn: 255991
* [mips][ias] Range check uimm10 operandsDaniel Sanders2015-12-091-4/+6
| | | | | | | | | | | | Summary: Reviewers: vkalintiris Subscribers: dsanders, llvm-commits Differential Revision: http://reviews.llvm.org/D15229 llvm-svn: 255112
* Revert r254897 "[mips][microMIPS] Implement LH, LHE, LHU and LHUE instructions"Zlatko Buljan2015-12-091-12/+0
| | | | | | | | | Commited patch was intended to implement LH, LHE, LHU and LHUE instructions. After commit test-suite failed with error message in the form of: fatal error: error in backend: Cannot select: t124: i32,ch = load<LD2[%d](tbaa=<0x94acc48>), sext from i16> t0, t2, undef:i32 For that reason I decided to revert commit r254897 and make new patch which besides implementation and standard regression tests will also have dedicated tests (CodeGen) for the above error. llvm-svn: 255109
* [mips][microMIPS] Implement LH, LHE, LHU and LHUE instructionsZlatko Buljan2015-12-071-0/+12
| | | | | | Differential Revision: http://reviews.llvm.org/D9824 llvm-svn: 254897
* [mips][ias] Range check uimm5 operands and fix several bugs this revealed.Daniel Sanders2015-11-261-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | Summary: The bugs were: * append, prepend, and balign were not tested * balign takes a uimm2 not a uimm5. * drotr32 was correctly implemented with a uimm5 but the tests expected '52' to be valid. * li/la were implemented with a uimm5 instead of simm32. simm32 isn't completely correct either but I'll fix that when I get to simm32. A notable omission are some of the shift instructions. Several of these have been implemented using a single uimm6 instruction (rather than two uimm5 instructions and a CodeGen-only uimm6 pseudo). These will be updated in the uimm6 patch. Reviewers: vkalintiris Subscribers: llvm-commits, dsanders Differential Revision: http://reviews.llvm.org/D14712 llvm-svn: 254164
* [mips][ias] Range check uimm3 operands.Daniel Sanders2015-11-061-0/+2
| | | | | | | | | | | | Summary: Reviewers: vkalintiris Subscribers: atanasyan, dsanders, llvm-commits Differential Revision: http://reviews.llvm.org/D14016 llvm-svn: 252296
* [mips][ias] Range check uimm2 operands and fix a bug this revealed.Daniel Sanders2015-11-062-2/+8
| | | | | | | | | | | | | | | Summary: The bug was that the MIPS32R6/MIPS64R6/microMIPS32R6 versions of LSA and DLSA (unlike the MSA version) failed to account for the off-by-one encoding of the immediate. The range is actually 1..4 rather than 0..3. Reviewers: vkalintiris Subscribers: atanasyan, dsanders, llvm-commits Differential Revision: http://reviews.llvm.org/D14015 llvm-svn: 252295
* [mips][microMIPS] Implement PREFX, LHUE, LBE, LBUE, LHE, LWE, SBE, SHE and ↵Zoran Jovanovic2015-09-162-1/+1
| | | | | | | | SWE instructions Differential Revision: http://reviews.llvm.org/D9189 llvm-svn: 247780
* [mips] Add support for branch-likely pseudo-instructionsZoran Jovanovic2015-09-151-4/+14
| | | | | | Differential Revision: http://reviews.llvm.org/D10537 llvm-svn: 247697
* [mips] Added support for various EVA ASE instructions.Daniel Sanders2015-09-153-9/+9
| | | | | | | | | | | | | | | | | | | | Summary: Added support for the following instructions: CACHEE, LBE, LBUE, LHE, LHUE, LWE, LLE, LWLE, LWRE, PREFE, SBE, SHE, SWE, SCE, SWLE, SWRE, TLBINV, TLBINVF This required adding some infrastructure for the EVA ASE. Patch by Scott Egerton. Reviewers: vkalintiris, dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D11139 llvm-svn: 247669
* [mips] Remap move as or.Vasileios Kalintiris2015-08-111-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | Summary: This patch remaps the assembly idiom 'move' to 'or' instead of 'daddu' or 'addu'. The use of addu/daddu instead of or as move was highlighted as a performance issue during the analysis of a recent 64bit design. Originally move was encoded as 'or' by binutils but was changed for the r10k cpu family due to their pipeline which had 2 arithmetic units and a single logical unit, and so could issue multiple (d)addu based moves at the same time but only 1 logical move. This patch preserves the disassembly behaviour so that disassembling a old style (d)addu move still appears as move, but assembling move always gives an or Patch by Simon Dardis. Reviewers: vkalintiris Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D11796 llvm-svn: 244579
* [mips] Added support for the ERETNC instruction.Vasileios Kalintiris2015-07-201-0/+1
| | | | | | | | | | | | | | Summary: This required adding the instruction predicate HasMips32r5. Patch by Scott Egerton. Reviewers: dsanders, vkalintiris Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D11136 llvm-svn: 242666
* [mips] Add COP0 register class and use it in M[FT]C0/DM[FT]C0.Daniel Sanders2015-06-271-0/+4
| | | | | | | | | | | | | | | | | Summary: Previously it (incorrectly) used GPR's. Patch by Simon Dardis. A couple small corrections by myself. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D10567 llvm-svn: 240883
* [mips64] Emit correct addend for some PC-relative relocationsPetar Jovanovic2015-06-231-20/+20
| | | | | | | | | | | So far, LLVM has not emitted correct addend for N64 and N32 ABI. This patch fixes that. It also removes fixup from MCJIT for R_MIPS_PC16 relocation. Patch by Vladimir Radosavljevic. Differential Revision: http://reviews.llvm.org/D10565 llvm-svn: 240404
* [mips] Change existing uimm10 operand to restrict the accepted immediatesZoran Jovanovic2015-06-111-0/+4
| | | | | | http://reviews.llvm.org/D10312 llvm-svn: 239520
* [mips][msa] Test basic operations for the N32 ABI too.Daniel Sanders2015-05-051-0/+3
| | | | | | | | | | | | | | | | | Summary: This required adding instruction aliases for dneg. N64 will be enabled shortly but requires additional bugfixes. Reviewers: vkalintiris Reviewed By: vkalintiris Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D9341 llvm-svn: 236489
* [mips][mips64r6] Sorted instructions in test. NFC.Daniel Sanders2015-04-301-96/+96
| | | | llvm-svn: 236221
* [mips] [IAS] Remove AssemblerPredicate's from RelocPIC and RelocStatic.Toma Tabacu2015-04-081-1/+8
| | | | | | | | | | | | | | | | Summary: These AssemblerPredicate's are unnecessary and actually make some instructions unusable when assembling pre-MIPS32 ISAs. For example, this was causing the IAS to reject the 'j' instruction for MIPS I-V. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8300 llvm-svn: 234398
* [mips] [IAS] Add support for the XOR $reg,imm pseudo-instruction.Toma Tabacu2015-03-171-0/+1
| | | | | | | | | | | | | | | | Summary: This adds a MipsInstAlias which expands to XORi $reg,$reg,imm. For example, "xor $6, 0x3A" should be expanded to "xori $6, $6, 58". This should work for all MIPS ISAs. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8284 llvm-svn: 232473
* Recommit "[mips] Add names and tests for the hardware registers"Vasileios Kalintiris2014-11-111-0/+6
| | | | | | | The original commit r221299 was reverted in r221307. I removed the name "hrw_ulr" ($29) from the original commit because two tests were failing. llvm-svn: 221681
* Revert "[mips] Add names and tests for the hardware registers"Rafael Espindola2014-11-041-6/+0
| | | | | | | | | | | | | This reverts commit r221299. The tests LLVM :: MC/Disassembler/Mips/mips32.txt LLVM :: MC/Disassembler/Mips/mips32_le.txt were failing. llvm-svn: 221307
* [mips] Add names and tests for the hardware registersVasileios Kalintiris2014-11-041-0/+6
| | | | | | | | | | | | Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D5763 llvm-svn: 221299
* [mips] Add support for COP1's Branch-On-Cond-Likely instructionsVasileios Kalintiris2014-10-174-6/+6
| | | | | | | | | | | | Summary: Depends on D5782 Reviewers: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D5802 llvm-svn: 220042
* [mips] Add support for COP0's Branch-On-Cond-Likely instructionsVasileios Kalintiris2014-10-172-8/+8
| | | | | | | | | | | | Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D5782 llvm-svn: 220036
* [mips] Marked the DI/EI instruction aliases as MIPS32r2Vasileios Kalintiris2014-10-161-0/+4
| | | | | | | | | | | | Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D5751 llvm-svn: 219927
* [mips] Improve the error messages given by MipsAsmParser.Toma Tabacu2014-09-165-80/+80
| | | | | | | | | | | | Summary: Changed error messages to be more informative and to resemble other clang/llvm error messages (first letter is lower case, no ending punctuation) and updated corresponding tests. Reviewers: dsanders Reviewed By: dsanders Differential Revision: http://reviews.llvm.org/D5065 llvm-svn: 217873
* [mips] Move 32-bit ADDiu instruction alias from Mips64InstrInfo.td to ↵Toma Tabacu2014-09-161-0/+1
| | | | | | | | | | MipsInstrInfo.td. Patch by Vasileios Kalintiris. Differential Revision: http://reviews.llvm.org/D5244 llvm-svn: 217868
* [mips] Marked the ADDi instruction aliases as not available in Mips32R6 and ↵Toma Tabacu2014-09-161-0/+4
| | | | | | | | | | Mips64R6. Patch by Vasileios Kalintiris. Differential Revision: http://reviews.llvm.org/D5242 llvm-svn: 217867
* [mips] Marked the DADDiu instruction aliases as MIPS III.Toma Tabacu2014-09-151-0/+4
| | | | | | | | Patch by Vasileios Kalintiris. Differential Revision: http://reviews.llvm.org/D5239 llvm-svn: 217770
* [mips] Marked the Trap-on-Condition instructions as Mips IIDaniel Sanders2014-09-051-0/+12
| | | | | | | | | | | | Patch by Vasileios Kalintiris. Reviewers: dsanders Reviewed By: dsanders Differential Revision: http://reviews.llvm.org/D5173 llvm-svn: 217255
* [mips][mips64r6] Correct cond names in the cmp.cond.[ds] instructionsDaniel Sanders2014-07-091-20/+20
| | | | | | | | | | Summary: It seems we accidentally read the wrong column of the table MIPS64r6 spec and used the names for c.cond.fmt instead of cmp.cond.fmt. Differential Revision: http://reviews.llvm.org/D4387 llvm-svn: 212607
* [mips][mips64r6] Correct the encoding of dmuh, dmuhu, dmul, and dmulu.Daniel Sanders2014-07-041-4/+4
| | | | | | | | We have detected a documentation bug in the encoding tables of the released MIPS64r6 specification that has resulted in the wrong encodings being used for these instructions in LLVM. This commit corrects them. llvm-svn: 212330
* [mips] Added support for assembling sdbbp.Daniel Sanders2014-06-241-0/+2
| | | | | | | | | | Summary: This instruction is re-encoded in MIPS32r6/MIPS64r6 without changing the restrictions. We hadn't implemented it for earlier ISA's so it has been added to those too. Differential Revision: http://reviews.llvm.org/D4265 llvm-svn: 211590
* ps][mips64r6] Added LSA/DLSA instructionsZoran Jovanovic2014-06-201-0/+2
| | | | | | Differential Revision: http://reviews.llvm.org/D3897 llvm-svn: 211346
* [mips] SYNC $stype instruction was added in Mips32Matheus Almeida2014-06-181-0/+2
| | | | | | but SYNC with an implied operand ($stype = 0) is valid since Mips2. llvm-svn: 211185
* [mips][mips64r6] Add BLTC and BLTUC instructionsZoran Jovanovic2014-06-181-0/+2
| | | | | | Differential Revision: http://reviews.llvm.org/D3923 llvm-svn: 211167
* [mips] Implement alias for 'and' and 'or' instructions for all ISAs.Matheus Almeida2014-06-181-0/+2
| | | | | | | | | | | | | | | Summary: Examples: and $2, 4 <=> andi $2, $2, 4 or $2, 4 <=> ori $2, $2, 4 Reviewers: dsanders Reviewed By: dsanders Differential Revision: http://reviews.llvm.org/D4155 llvm-svn: 211161
* [mips][mips64r6] ssnop is deprecated on MIPS32r6/MIPS64r6Daniel Sanders2014-06-161-1/+4
| | | | | | | | | | | | Summary: Depends on D4120 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: zoran.jovanovic, vmedic Differential Revision: http://reviews.llvm.org/D4121 llvm-svn: 211021
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