| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | [mips] Support 64-bit offsets for lb/sb/ld/sd/lld ... instructions | Simon Atanasyan | 2018-06-01 | 1 | -14/+0 |
| * | [mips] Accept 32-bit offsets for ld/sd/lld commands | Simon Atanasyan | 2018-05-10 | 1 | -6/+6 |
| * | [mips] Accept 32-bit offsets for lh and lhu commands | Simon Atanasyan | 2018-05-10 | 1 | -4/+4 |
| * | [mips] Accept 32-bit offsets for lb and lbu commands | Simon Atanasyan | 2018-04-26 | 1 | -4/+4 |
| * | [mips] Show an error if register number is out of range | Simon Atanasyan | 2018-04-24 | 1 | -26/+26 |
| * | [AArch64][SVE] Re-submit patch series for ZIP1/ZIP2 | Sander de Smalen | 2017-12-20 | 1 | -6/+6 |
| * | Revert "[AArch64][SVE] Asm" changes, they broke libjpeg_turbo | Reid Kleckner | 2017-12-18 | 1 | -6/+6 |
| * | [TableGen][AsmMatcherEmitter] Only choose specific diagnostic for enabled ins... | Sander de Smalen | 2017-12-18 | 1 | -6/+6 |
| * | [mips] Add test cases for dext/dins family of instructions | Aleksandar Beserminji | 2017-09-29 | 1 | -0/+25 |
| * | [mips] Implement the 'dext' aliases and it's disassembly alias. | Simon Dardis | 2017-09-14 | 1 | -0/+4 |
| * | [mips][microMIPS] add lapc instruction | Petar Jovanovic | 2017-09-11 | 1 | -0/+4 |
| * | [mips] Fix aui/daui/dahi/dati for MIPSR6 | Simon Dardis | 2016-10-14 | 1 | -0/+13 |
| * | [mips] Add IAS support for dvp, evp | Simon Dardis | 2016-10-13 | 1 | -0/+6 |
| * | Revert "[mips] Fix aui/daui/dahi/dati for MIPSR6" | Simon Dardis | 2016-09-16 | 1 | -13/+0 |
| * | [mips] Fix aui/daui/dahi/dati for MIPSR6 | Simon Dardis | 2016-09-16 | 1 | -0/+13 |
| * | [mips][microMIPS] Implement BLTZC, BLEZC, BGEZC and BGTZC instructions, fix d... | Hrvoje Varga | 2016-08-22 | 1 | -0/+48 |
| * | [mips][ias] Check '$rs = $rd' constraints when both registers are in AsmText. | Daniel Sanders | 2016-07-27 | 1 | -0/+1 |
| * | [mips][microMIPS] Implement LDC1, SDC1, LDC2, SDC2, LWC1, SWC1, LWC2 and SWC2... | Zlatko Buljan | 2016-07-11 | 1 | -0/+36 |
| * | [mips][micromips] Implement LD, LLD, LWU, SD, DSRL, DSRL32 and DSRLV instruct... | Hrvoje Varga | 2016-06-27 | 1 | -0/+16 |
| * | [mips] Enforce compact branch register restrictions | Simon Dardis | 2016-05-31 | 1 | -1/+15 |
| * | [mips][microMIPS] Implement LH, LHE, LHU and LHUE instructions and add CodeGe... | Zlatko Buljan | 2016-05-18 | 1 | -0/+16 |
| * | Revert "[mips][microMIPS] Implement CFC*, CTC* and LDC* instructions" | Hrvoje Varga | 2016-05-12 | 1 | -2/+1 |
| * | [mips][microMIPS] Implement CFC*, CTC* and LDC* instructions | Hrvoje Varga | 2016-05-11 | 1 | -1/+2 |
| * | [mips][microMIPS] Revert commit r266861. | Zoran Jovanovic | 2016-04-22 | 1 | -2/+1 |
| * | [mips][microMIPS]Implement CFC*, CTC* and LDC* instructions | Hrvoje Varga | 2016-04-20 | 1 | -1/+2 |
| * | [mips] Invalid tests for MTC0, MTC2, MFC0, MFC2, DMTC0, DMFC0 MIPS instructions | Hrvoje Varga | 2016-03-11 | 1 | -0/+4 |
| * | [mips][microMIPS][DSP] Implement PACKRL.PH, PICK.PH, PICK.QB, SHILO, SHILOV a... | Zlatko Buljan | 2015-12-18 | 1 | -0/+1 |
| * | [mips][ias] Range check uimm10 operands | Daniel Sanders | 2015-12-09 | 1 | -4/+6 |
| * | Revert r254897 "[mips][microMIPS] Implement LH, LHE, LHU and LHUE instructions" | Zlatko Buljan | 2015-12-09 | 1 | -12/+0 |
| * | [mips][microMIPS] Implement LH, LHE, LHU and LHUE instructions | Zlatko Buljan | 2015-12-07 | 1 | -0/+12 |
| * | [mips][ias] Range check uimm5 operands and fix several bugs this revealed. | Daniel Sanders | 2015-11-26 | 1 | -0/+8 |
| * | [mips][ias] Range check uimm3 operands. | Daniel Sanders | 2015-11-06 | 1 | -0/+2 |
| * | [mips][ias] Range check uimm2 operands and fix a bug this revealed. | Daniel Sanders | 2015-11-06 | 1 | -0/+6 |
| * | [mips] Add support for branch-likely pseudo-instructions | Zoran Jovanovic | 2015-09-15 | 1 | -4/+14 |
| * | [mips] Change existing uimm10 operand to restrict the accepted immediates | Zoran Jovanovic | 2015-06-11 | 1 | -0/+4 |
| * | [mips][mips64r6] [ls][wd]c2 were re-encoded with 11-bit signed immediates rat... | Daniel Sanders | 2014-06-16 | 1 | -2/+4 |
| * | [mips] Implement jr.hb and jalr.hb (Jump Register and Jump and Link Register ... | Matheus Almeida | 2014-06-11 | 1 | -0/+10 |
