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* Migrate function attribute "no-frame-pointer-elim" to "frame-pointer"="all" ↵Fangrui Song2019-12-241-2/+2
| | | | as cleanups after D56351
* [llvm-mc] Add reportWarning() to MCContextBrian Cain2019-08-081-0/+19
| | | | | | | Adding reportWarning() to MCContext, so that it can be used from the Hexagon assembler backend. llvm-svn: 368327
* [lit] Delete empty lines at the end of lit.local.cfg NFCFangrui Song2019-06-171-1/+0
| | | | llvm-svn: 363538
* [llvm-objdump] - Print relocation record in a GNU format.George Rimar2019-05-071-1/+1
| | | | | | | | | | | | | | | This fixes the https://bugs.llvm.org/show_bug.cgi?id=41355. Previously with -r we printed relocation section name instead of the target section name. It was like this: "RELOCATION RECORDS FOR [.rel.text]" Now it is: "RELOCATION RECORDS FOR [.text]" Also when relocation target section has more than one relocation section, we did not combine the output. Now we do. Differential revision: https://reviews.llvm.org/D61312 llvm-svn: 360143
* [hexagon] change AsmParser assertion to errorBrian Cain2019-05-032-0/+12
| | | | | | | For immediates that can't be evaluated in assembler-mapped instructions, we should return 'invalid operand' instead of assert. llvm-svn: 359905
* [llvm-readobj] Change -long-option to --long-option in tests. NFCFangrui Song2019-05-011-4/+4
| | | | | | | | | | We use both -long-option and --long-option in tests. Switch to --long-option for consistency. In the "llvm-readelf" mode, -long-option is discouraged as it conflicts with grouped short options and it is not accepted by GNU readelf. While updating the tests, change llvm-readobj -s to llvm-readobj -S to reduce confusion ("s" is --section-headers in llvm-readobj but --symbols in llvm-readelf). llvm-svn: 359649
* [Hexagon] Add instruction definitions for Hexagon V66Krzysztof Parzyszek2018-12-053-0/+39
| | | | llvm-svn: 348411
* [MC] Fix 3 objdump tests after rL346610Fangrui Song2018-11-112-6/+6
| | | | llvm-svn: 346617
* [Hexagon] Handle Hexagon's SHF_HEX_GPREL section flagKrzysztof Parzyszek2018-11-091-0/+10
| | | | llvm-svn: 346494
* [Hexagon] Remove support for V4Krzysztof Parzyszek2018-10-191-2/+0
| | | | llvm-svn: 344791
* Check for tied operandsSid Manning2018-08-131-0/+6
| | | | | | Differential Revision: https://reviews.llvm.org/D50592 llvm-svn: 339567
* [Hexagon] Fix the value of HexagonII::TypeCVI_FIRSTKrzysztof Parzyszek2018-06-191-0/+12
| | | | | | | | | This value is the first vector instruction type in numerical order. The previous value was incorrect, leaving TypeCVI_GATHER outside of the range for vector instructions. This caused vector .new instructions to be incorrectly encoded in the presence of gather. llvm-svn: 335065
* [Hexagon] Use addAliasForDirective for data directivesAlex Bradbury2018-05-172-0/+45
| | | | | | | | | | | Data directives such as .word, .half, .hword are currently parsed using HexagonAsmParser::ParseDirectiveValue which effectively duplicates logic from AsmParser::parseDirectiveValue. This patch deletes that duplicated logic in favour of using addAliasForDirective. Differential Revision: https://reviews.llvm.org/D46999 llvm-svn: 332607
* Hexagon: Put relocations after instructions not packets.Sid Manning2018-05-142-2/+17
| | | | | | | | | | | | | Change relocation output so that relocation information follows individual instructions rather than clustering them at the end of packets. This change required shifting block of code but the actual change is in HexagonPrettyPrinter's PrintInst. Differential Revision: https://reviews.llvm.org/D46728 llvm-svn: 332283
* [Hexagon] Move clamping of extended operands directly to MC code emitterKrzysztof Parzyszek2018-05-071-0/+7
| | | | llvm-svn: 331653
* [Hexagon] Recognize and handle :endloop01Krzysztof Parzyszek2018-03-301-3/+10
| | | | llvm-svn: 328870
* [Hexagon] Always generate mux out of predicated transfers if possibleKrzysztof Parzyszek2018-03-231-4/+3
| | | | | | | | | | | | HexagonGenMux would collapse pairs of predicated transfers if it assumed that the predicated .new forms cannot be created. Turns out that generating mux is preferable in almost all cases. Introduce an option -hexagon-gen-mux-threshold that controls the minimum distance between the instruction defining the predicate and the later of the two transfers. If the distance is closer than the threshold, mux will not be generated. Set the threshold to 0 by default. llvm-svn: 328346
* [Hexagon] Add trap1 instructionKrzysztof Parzyszek2018-03-012-1/+13
| | | | llvm-svn: 326492
* [Hexagon] Add guest registersKrzysztof Parzyszek2018-03-011-0/+67
| | | | llvm-svn: 326450
* [Hexagon] Express calling conventions via .td file instead of hand-codingKrzysztof Parzyszek2018-02-091-4/+4
| | | | | | Additionally, simplify the rest of the argument/parameter lowering code. llvm-svn: 324737
* [Hexagon] Add support for Hexagon V65Krzysztof Parzyszek2017-12-118-21/+250
| | | | llvm-svn: 320404
* [Hexagon] Remove trailing spaces, NFCKrzysztof Parzyszek2017-11-223-4/+4
| | | | llvm-svn: 318875
* [Hexagon] New HVX target features.Sumanth Gundapaneni2017-10-1813-22/+22
| | | | | | | | | | | | | | | | | | | | | | This patch lets the llvm tools handle the new HVX target features that are added by frontend (clang). The target-features are of the form "hvx-length64b" for 64 Byte HVX mode, "hvx-length128b" for 128 Byte mode HVX. "hvx-double" is an alias to "hvx-length128b" and is soon will be deprecated. The hvx version target feature is upgated form "+hvx" to "+hvxv{version_number}. Eg: "+hvxv62" For the correct HVX code generation, the user must use the following target features. For 64B mode: "+hvxv62" "+hvx-length64b" For 128B mode: "+hvxv62" "+hvx-length128b" Clang picks a default length if none is specified. If for some reason, no hvx-length is specified to llvm, the compilation will bail out. There is a corresponding clang patch. Differential Revision: https://reviews.llvm.org/D38851 llvm-svn: 316101
* [Hexagon] Handle a global operand to A2_addi when creating duplexesKrzysztof Parzyszek2017-06-221-0/+15
| | | | llvm-svn: 306012
* [Hexagon] Change iconst to emit 27bit relocationKrzysztof Parzyszek2017-05-021-1/+1
| | | | | | Patch by Colin LeMahieu. llvm-svn: 301956
* [Hexagon] Add extenders for GD_PLT_B22_PCREL and LD_PLT_B22_PCRELKrzysztof Parzyszek2017-05-021-0/+13
| | | | | | Patch by Sid Manning. llvm-svn: 301955
* [Hexagon] Make sure duplexed dealloc_returns are checked for double jumpsKrzysztof Parzyszek2017-05-021-0/+7
| | | | | | Patch by Colin LeMahieu. llvm-svn: 301951
* [Hexagon] Move checking AXOK to checkerKrzysztof Parzyszek2017-05-022-0/+13
| | | | | | Patch by Colin LeMahieu. llvm-svn: 301949
* [Hexagon] Extract function that checks endloops with other branchesKrzysztof Parzyszek2017-05-022-19/+12
| | | | | | | | Change location number to point to conflicting branch instruction. Patch by Colin LeMahieu. llvm-svn: 301946
* [Hexagon] Improving error reporting for writing to read only registersKrzysztof Parzyszek2017-05-014-0/+25
| | | | | | Patch by Colin LeMahieu. llvm-svn: 301828
* [Hexagon] Give better error messages for solo instruction errorsKrzysztof Parzyszek2017-05-012-0/+15
| | | | | | Patch by Colin LeMahieu. llvm-svn: 301827
* [Hexagon] Fixing test from 297920 to add Hexagon triple.Colin LeMahieu2017-03-161-2/+2
| | | | llvm-svn: 297926
* [Hexagon] Updating inline saturate lanes for v62 version.Colin LeMahieu2017-03-161-0/+13
| | | | llvm-svn: 297920
* [Hexagon] Fix testcase accidentally broken by r296645Krzysztof Parzyszek2017-03-011-2/+2
| | | | llvm-svn: 296647
* [Hexagon] Introduce Hexagon V62Krzysztof Parzyszek2017-02-105-0/+630
| | | | llvm-svn: 294805
* [Hexagon] Replace instruction definitions with auto-generated onesKrzysztof Parzyszek2017-02-1022-209/+206
| | | | llvm-svn: 294753
* [Hexagon] Remove encoding bits from mapped instructionsKrzysztof Parzyszek2017-02-071-4/+4
| | | | | | | | | | - Map A2_zxtb to A2_andir. - Map PS_call_nr J2_call. - Map A2_tfr[t|f][new] to A2_padd[t|f][new]. Patch by Colin LeMahieu. llvm-svn: 294320
* [Hexagon] Adding gp+ to the syntax of gp-relative instructionsKrzysztof Parzyszek2017-02-069-13/+652
| | | | | | Patch by Colin LeMahieu. llvm-svn: 294258
* [Hexagon] Update MCTargetDescKrzysztof Parzyszek2017-02-0613-10/+164
| | | | | | | | | | Changes include: - Updates to the instruction descriptor flags. - Improvements to the packet shuffler and checker. - Updates to the handling of certain relocations. - Better handling of duplex instructions. llvm-svn: 294226
* [Hexagon] Adding opExtentBits and opExtentAlign to GPrel instructionsKrzysztof Parzyszek2017-02-021-4/+4
| | | | | | Patch by Colin LeMahieu. llvm-svn: 293933
* [Hexagon] Fix relocation kind for extended predicated callsKrzysztof Parzyszek2017-02-021-0/+6
| | | | | | Patch by Sid Manning. llvm-svn: 293931
* [Hexagon] Fix disassembler crash after r279255Krzysztof Parzyszek2016-09-091-0/+7
| | | | | | | When p0 was added as an explicit operand to the duplex subinstructions, the disassembler was not updated to reflect this. llvm-svn: 281104
* Remove redundant -mattr options from llvm-objdump commands.Daniel Sanders2016-06-161-1/+1
| | | | | | | | The -mattr options in these four tests have no effect on the output of llvm-objdump. In the case of the two Mips tests, removing the -mattr option left duplicate RUN lines so the duplicates have been removed. llvm-svn: 272906
* [Hexagon] Use pipe instead of temporary files in testsKrzysztof Parzyszek2016-05-203-6/+6
| | | | llvm-svn: 270217
* [Hexagon] Treat all conditional branches as predicted (not-taken by default)Krzysztof Parzyszek2016-05-091-0/+14
| | | | llvm-svn: 268946
* [Hexagon] Add aliases for vector loads/stores with no explicit offsetKrzysztof Parzyszek2016-05-051-0/+61
| | | | | | The mem(r0) instructions are treated as mem(r0+#0). llvm-svn: 268661
* [Hexagon] Add instruction aliases for vector unsigned compare-equalKrzysztof Parzyszek2016-04-281-0/+36
| | | | | | Unsigned compare-equal instructions are mapped to signed compare-equal. llvm-svn: 267925
* [Hexagon] Define certain aliases for vector instructionsKrzysztof Parzyszek2016-04-281-0/+10
| | | | | | | | | Specifically: Vd = #0 -> Vd = vxor(Vd, Vd) Vdd = #0 -> Vdd.w = vsub(Vdd.w, Vdd.w) Vdd = Vss -> Vdd = vcombine(Vss.H, Vss.L) llvm-svn: 267901
* [Hexagon] Handle double-vector registers as new-value producersKrzysztof Parzyszek2016-04-281-0/+12
| | | | | | Patch by Colin LeMahieu. llvm-svn: 267897
* [Hexagon] Merging nops in to previous packet rather than always creating a ↵Colin LeMahieu2016-04-271-0/+60
| | | | | | new one. llvm-svn: 267798
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