summaryrefslogtreecommitdiffstats
path: root/llvm/test/MC/Hexagon
Commit message (Collapse)AuthorAgeFilesLines
...
* [Hexagon] Use llvm-mc instead of llc in an MC testcaseKrzysztof Parzyszek2016-04-251-0/+9
| | | | | | Remember to svn add the new file. llvm-svn: 267435
* [Hexagon] Use llvm-mc instead of llc in an MC testcaseKrzysztof Parzyszek2016-04-251-9/+0
| | | | llvm-svn: 267434
* [Hexagon] Correctly set "Flags" in ELF headerKrzysztof Parzyszek2016-04-251-0/+9
| | | | llvm-svn: 267397
* [Hexagon] Add definitions for trap/pause instructionsKrzysztof Parzyszek2016-04-221-0/+36
| | | | | | Also add tests for other instructions from HexagonSystemInst.td. llvm-svn: 267162
* [Hexagon] Properly recognize register alt namesKrzysztof Parzyszek2016-04-211-0/+14
| | | | llvm-svn: 267038
* [Hexagon] Fix handling of lcomm directiveKrzysztof Parzyszek2016-04-201-0/+19
| | | | | | Patch by Colin LeMahieu. llvm-svn: 266882
* Revert r265817Colin LeMahieu2016-04-0810-10/+10
| | | | | | lld tests need to be addressed. llvm-svn: 265822
* [llvm-objdump] Printing hex instead of dec by defaultColin LeMahieu2016-04-0810-10/+10
| | | | | | Differential Revision: http://reviews.llvm.org/D18770 llvm-svn: 265817
* [Hexagon] Add handling fixups and instruction relaxationKrzysztof Parzyszek2016-03-211-0/+25
| | | | llvm-svn: 263981
* [Hexagon] Properly encode registers in duplex instructionsKrzysztof Parzyszek2016-03-211-0/+10
| | | | llvm-svn: 263980
* [Hexagon] As a size optimization, not lazy extending TPREL or DTPREL ↵Colin LeMahieu2016-02-291-0/+8
| | | | | | variants since they're usually in range. llvm-svn: 262258
* [Hexagon] Adding relocation for code size, cold path optimization allowing a ↵Colin LeMahieu2016-02-161-0/+6
| | | | | | | | | | | | 23-bit 4-byte aligned relocation to be a valid instruction encoding. The usual way to get a 32-bit relocation is to use a constant extender which doubles the size of the instruction, 4 bytes to 8 bytes. Another way is to put a .word32 and mix code and data within a function. The disadvantage is it's not a valid instruction encoding and jumping over it causes prefetch stalls inside the hardware. This relocation packs a 23-bit value in to an "r0 = add(rX, #a)" instruction by overwriting the source register bits. Since r0 is the return value register, if this instruction is placed after a function call which return void, r0 will be filled with an undefined value, the prefetch won't be confused, and the callee can access the constant value by way of the link register. llvm-svn: 261006
* [llvm-readobj] Option to emit readelf like outputHemant Kulkarni2016-02-101-1/+1
| | | | | | | | | New option --elf-output-style=LLVM or GNU Enables -file-headers in readelf style when elf-output-style=GNU Differential revision: http://reviews.llvm.org/D14128 llvm-svn: 260430
* Revert "[llvm-readobj] Option to emit readelf like output"Hemant Kulkarni2016-02-101-1/+1
| | | | | | This reverts commit a58765909660a7195b32e0cc8c7476168b913750. llvm-svn: 260397
* [llvm-readobj] Option to emit readelf like outputHemant Kulkarni2016-02-101-1/+1
| | | | | | | | | New option --elf-output-style=LLVM or GNU Enables -file-headers in readelf style when elf-output-style=GNU Differential revision: http://reviews.llvm.org/D14128 llvm-svn: 260391
* [Hexagon] Fixing relocation generation and adding tests.Colin LeMahieu2016-02-091-0/+244
| | | | llvm-svn: 260259
* Fix several accidental DOS line endings in source filesDimitry Andric2016-01-031-3/+3
| | | | | | | | | | | | | | | Summary: There are a number of files in the tree which have been accidentally checked in with DOS line endings. Convert these to native line endings. There are also a few files which have DOS line endings on purpose, and I have set the svn:eol-style property to 'CRLF' on those. Reviewers: joerg, aaron.ballman Subscribers: aaron.ballman, sanjoy, dsanders, llvm-commits Differential Revision: http://reviews.llvm.org/D15848 llvm-svn: 256707
* [Hexagon] Add PIC supportKrzysztof Parzyszek2015-12-182-0/+22
| | | | llvm-svn: 256025
* [Hexagon] Adding shuffling resources for HVX instructions and tests for ↵Colin LeMahieu2015-12-039-0/+1189
| | | | | | instruction encodings. llvm-svn: 254652
* [Hexagon] NFC. Adding a number of packet correctness tests.Colin LeMahieu2015-11-135-0/+88
| | | | llvm-svn: 253000
* [Hexagon] Adding relaxation functionality to backend and test.Colin LeMahieu2015-11-132-0/+25
| | | | llvm-svn: 252989
* [Hexagon] Adding checks for values out of operand range and correct ↵Colin LeMahieu2015-11-122-0/+82
| | | | | | new-value producer usage. llvm-svn: 252969
* [Hexagon] Adding test to make sure labels and register pairs are correctly ↵Colin LeMahieu2015-11-121-0/+26
| | | | | | parsed. llvm-svn: 252968
* [Hexagon] Adding instruction aliases and tests.Colin LeMahieu2015-11-101-0/+608
| | | | llvm-svn: 252579
* [Hexagon] Fixing compound register printing and reenabling more tests.Colin LeMahieu2015-11-101-1/+0
| | | | llvm-svn: 252574
* [Hexagon] Fixing store instructions and reenabling a few more tests.Colin LeMahieu2015-11-101-1/+0
| | | | llvm-svn: 252561
* [Hexagon] Fixing load instruction parsing and reenabling tests.Colin LeMahieu2015-11-101-6/+0
| | | | llvm-svn: 252555
* [Hexagon] Enabling ASM parsing on Hexagon backend and adding instruction ↵Colin LeMahieu2015-11-0920-0/+3842
| | | | | | parsing tests. General updating of the code emission. llvm-svn: 252443
* [Hexagon] Split double registersKrzysztof Parzyszek2015-10-163-3/+3
| | | | llvm-svn: 250549
* [Hexagon] Reapply r239097 with tests corrected for shuffling and duplexing.Colin LeMahieu2015-06-056-18/+21
| | | | llvm-svn: 239161
* [Hexagon] Disassembling, printing, and emitting instructions a whole-bundle ↵Colin LeMahieu2015-05-298-16/+32
| | | | | | at a time which is the semantic unit for Hexagon. Fixing tests to use the new format. Disabling tests in the direct object emission path for a followup patch. llvm-svn: 238556
* Expand MUX instructions early on HexagonKrzysztof Parzyszek2015-03-311-1/+1
| | | | | | This time with all files included. llvm-svn: 233696
* Revert 233694. Weak SVN-fu.Krzysztof Parzyszek2015-03-311-1/+1
| | | | llvm-svn: 233695
* Expand MUX instructions early on HexagonKrzysztof Parzyszek2015-03-311-1/+1
| | | | llvm-svn: 233694
* [Hexagon] Updating predicate register transfers and adding tstbit to allow ↵Colin LeMahieu2014-12-099-9/+9
| | | | | | select selection. Updating ll tests with predicate transfers that previously had nop encodings. llvm-svn: 223800
* [Hexagon] Adding cmp* immediate form instructions.Colin LeMahieu2014-11-263-0/+30
| | | | llvm-svn: 222849
* [Hexagon] Adding and64, or64, and xor64 instructions.Colin LeMahieu2014-11-263-0/+30
| | | | llvm-svn: 222846
* [Hexagon] Adding add64 and sub64 instructions.Colin LeMahieu2014-11-252-0/+20
| | | | llvm-svn: 222795
* Reverting 222792Colin LeMahieu2014-11-253-30/+0
| | | | llvm-svn: 222793
* [Hexagon] Adding compare with immediate instructions.Colin LeMahieu2014-11-253-0/+30
| | | | llvm-svn: 222792
* [Hexagon] [NFC] Adding trailing whitespace to test files.Colin LeMahieu2014-11-2517-17/+17
| | | | llvm-svn: 222785
* [Hexagon] Adding C2_mux instruction.Colin LeMahieu2014-11-251-0/+10
| | | | llvm-svn: 222784
* [Hexagon] Replacing cmp* instructions with ones that contain encoding bits.Colin LeMahieu2014-11-255-0/+50
| | | | llvm-svn: 222771
* [Hexagon] Adding asrh instruction, removing unused multiclasses.Colin LeMahieu2014-11-241-0/+10
| | | | llvm-svn: 222670
* [Hexagon] Adding aslh instruction.Colin LeMahieu2014-11-241-0/+10
| | | | llvm-svn: 222668
* [Hexagon] Adding zxth instruction.Colin LeMahieu2014-11-241-0/+10
| | | | llvm-svn: 222662
* [Hexagon] Adding zxtb instruction.Colin LeMahieu2014-11-241-0/+10
| | | | llvm-svn: 222660
* [Hexagon] Adding sxth instruction.Colin LeMahieu2014-11-211-0/+10
| | | | llvm-svn: 222577
* [Hexagon] Adding sxtb instruction. Renaming some identically named classes ↵Colin LeMahieu2014-11-211-0/+10
| | | | | | that will be removed after converting referencing defs. llvm-svn: 222575
* [Hexagon] Adding A2_xor instruction with IR selection pattern and test.Colin LeMahieu2014-11-191-0/+10
| | | | llvm-svn: 222399
OpenPOWER on IntegriCloud