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* [Power9] Implement new vector compare, extract, insert instructionsKit Barton2016-03-011-0/+80
| | | | | | | | | | | | | | | | | | This change implements the following vector operations: - Vector Compare Not Equal - vcmpneb(.) vcmpneh(.) vcmpnew(.) - vcmpnezb(.) vcmpnezh(.) vcmpnezw(.) - Vector Extract Unsigned - vextractub vextractuh vextractuw vextractd - vextublx vextubrx vextuhlx vextuhrx vextuwlx vextuwrx - Vector Insert - vinsertb vinserth vinsertw vinsertd 26 instructions. Phabricator: http://reviews.llvm.org/D15916 llvm-svn: 262392
* [mips] Range check uimm20 and fixed a bug this revealed.Daniel Sanders2016-02-291-3/+3
| | | | | | | | | | | | | | | | | | | Summary: The bug was that dextu's operand 3 would print 0-31 instead of 32-63 when printing assembly. This came up when replacing MipsInstPrinter::printUnsignedImm() with a version that could handle arbitrary bit widths. MipsAsmPrinter::printUnsignedImm*() don't seem to be used so they have been removed. Reviewers: vkalintiris Subscribers: dsanders, llvm-commits Differential Revision: http://reviews.llvm.org/D15521 llvm-svn: 262231
* The patch adds missing registers and instructions to complete all the ↵Chris Dewhurst2016-02-271-0/+12
| | | | | | | | | | | | | registers supported by the Sparc v8 manual. These are all co-processor registers, with the exception of the floating-point deferred-trap queue register. Although these will not be lowered automatically by any instructions, it allows the use of co-processor instructions implemented by inline-assembly. Code Reviewed at http://reviews.llvm.org/D17133, with the exception of a very small change in brace placement in SparcInstrInfo.td, which was formerly causing a problem in the disassembly of the %fq register. llvm-svn: 262133
* Power9] Implement new vsx instructions: compare and conversionKit Barton2016-02-261-0/+86
| | | | | | | | | | | | | | | | | | | This change implements the following vsx instructions: Quad/Double-Precision Compare: xscmpoqp xscmpuqp xscmpexpdp xscmpexpqp xscmpeqdp xscmpgedp xscmpgtdp xscmpnedp xvcmpnedp(.) xvcmpnesp(.) Quad-Precision Floating-Point Conversion xscvqpdp(o) xscvdpqp xscvqpsdz xscvqpswz xscvqpudz xscvqpuwz xscvsdqp xscvudqp xscvdphp xscvhpdp xvcvhpsp xvcvsphp xsrqpi xsrqpix xsrqpxp 28 instructions Phabricator: http://reviews.llvm.org/D16709 llvm-svn: 262068
* Reverting breaking change. Sorry.Chris Dewhurst2016-02-261-12/+0
| | | | llvm-svn: 262007
* Reviewed at reviews.llvm.org/D17133Chris Dewhurst2016-02-261-0/+12
| | | | llvm-svn: 262005
* [AMDGPU] Disassembler: Support for all VOP1 instructions.Nikolay Haustov2016-02-251-0/+250
| | | | | | | | | | | | | | | Support all instructions with VOP1 encoding with 32 or 64-bit operands for VI subtarget: VGPR_32 and VReg_64 operand register classes VS_32 and VS_64 operand register classes with inline and literal constants Tests for VOP1 instructions. Patch by: skolton Reviewers: arsenm, tstellarAMD Review: http://reviews.llvm.org/D17194 llvm-svn: 261878
* AVX512F: Add GATHER/SCATTER assembler Intel syntax tests for knl/skx/avx . ↵Igor Breger2016-02-251-2/+2
| | | | | | | | Change memory operand parser handling. Differential Revision: http://reviews.llvm.org/D17564 llvm-svn: 261862
* [mips][microMIPS] Implement DINSU, DINSM, DINS instructionsHrvoje Varga2016-02-251-0/+3
| | | | | | Differential Revision: http://reviews.llvm.org/D16181 llvm-svn: 261860
* [X86] Add some missing reversed forms of XOP instructions.Craig Topper2016-02-201-0/+9
| | | | llvm-svn: 261417
* [mips][microMIPS] Implement TLBINV and TLBINVF instructionsZlatko Buljan2016-02-182-0/+4
| | | | | | Differential Revision: http://reviews.llvm.org/D16849 llvm-svn: 261211
* [AMDGPU] Disassembler: Added basic disassembler for AMDGPU targetTom Stellard2016-02-183-0/+37
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Changes: - Added disassembler project - Fixed all decoding conflicts in .td files - Added DecoderMethod=“NONE” option to Target.td that allows to disable decoder generation for an instruction. - Created decoding functions for VS_32 and VReg_32 register classes. - Added stubs for decoding all register classes. - Added several tests for disassembler Disassembler only supports: - VI subtarget - VOP1 instruction encoding - 32-bit register operands and inline constants [Valery] One of the point that requires to pay attention to is how decoder conflicts were resolved: - Groups of target instructions were separated by using different DecoderNamespace (SICI, VI, CI) using similar to AssemblerPredicate approach. - There were conflicts in IMAGE_<> instructions caused by two different reasons: 1. dmask wasn’t specified for the output (fixed) 2. There are image instructions that differ only by the number of the address components but have the same encoding by the HW spec. The actual number of address components is determined by the HW at runtime using image resource descriptor starting from the VGPR encoded in an IMAGE instruction. This means that we should choose only one instruction from conflicting group to be the rule for decoder. I didn’t find the way to disable decoder generation for an arbitrary instruction and therefore made a onelinear fix to tablegen generator that would suppress decoder generation when DecoderMethod is set to “NONE”. This is a change that should be reviewed and submitted first. Otherwise I would need to specify different DecoderNamespace for every instruction in the conflicting group. I haven’t checked yet if DecoderMethod=“NONE” is not used in other targets. 3. IMAGE_GATHER decoder generation is for now disabled and to be done later. [/Valery] Patch By: Sam Kolton Differential Revision: http://reviews.llvm.org/D16723 llvm-svn: 261185
* [mips] Range check uimm16 and fix several bugs this revealed.Daniel Sanders2016-02-0114-70/+70
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: The bugs were: * teq and similar take 4-bit unsigned immediates on microMIPS. * teqi and similar have side-effects like teq do. * shll_s.w and shra_r.w take 5-bit unsigned immediates. * The various DSP ext* instructions take a 5-bit immediate. * repl.qh takes an 8-bit unsigned immediate. * repl.ph takes a 10-bit unsigned immediate. * rddsp/wrdsp take a 10-bit unsigned immediate. * teqi and similar take signed 16-bit immediates (10-bit for microMIPS). * Out-of-range immediate macros for or/xor take a simm32/simm64 depending on architecture. I'll fix the simm64 case properly when I reach simm32. lui is a bit more lenient than GAS and accepts signed immediates in addition to unsigned. This is because MipsMCExpr can produce signed values when constant folding and it currently lacks a way of knowing it should fold to an unsigned value. Reviewers: vkalintiris Subscribers: dsanders, llvm-commits Differential Revision: http://reviews.llvm.org/D15446 llvm-svn: 259360
* [ARM] Add new system registers to ARMv8-M Baseline/MainlineBradley Smith2016-01-251-0/+25
| | | | | | | | This patch was originally committed as r257884, but was reverted due to windows failures. The cause of these failures has been fixed under r258677, hence re-committing the original patch. llvm-svn: 258682
* [ARM] Add ARMv8.2-A FP16 scalar instructionsOliver Stannard2016-01-254-0/+746
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This was originally committed as r255762, but reverted as it broke windows bots. Re-commitiing the exact same patch, as the underlying cause was fixed by r258677. ARMv8.2-A adds 16-bit floating point versions of all existing VFP floating-point instructions. This is an optional extension, so all of these instructions require the FeatureFullFP16 subtarget feature. The assembly for these instructions uses S registers (AArch32 does not have H registers), but the instructions have ".f16" type specifiers rather than ".f32" or ".f64". The top 16 bits of each source register are ignored, and the top 16 bits of the destination register are set to zero. These instructions are mostly the same as the 32- and 64-bit versions, but they use coprocessor 9 rather than 10 and 11. Two new instructions, VMOVX and VINS, have been added to allow packing and extracting two 16-bit floats stored in the top and bottom halves of an S register. New fixup kinds have been added for the PC-relative load and store instructions, but no ELF relocations have been added as they have a range of 512 bytes. Differential Revision: http://reviews.llvm.org/D15038 llvm-svn: 258678
* # This is a combination of 2 commits.Reid Kleckner2016-01-151-25/+0
| | | | | | | | | | | | | | | | # The first commit's message is: Revert "[ARM] Add DSP build attribute and extension targeting" This reverts commit b11cc50c0b4a7c8cdb628abc50b7dc226ff583dc. # This is the 2nd commit message: Revert "[ARM] Add new system registers to ARMv8-M Baseline/Mainline" This reverts commit 837d08454e3e5beb8581951ac26b22fa07df3cd5. llvm-svn: 257916
* [ARM] Add new system registers to ARMv8-M Baseline/MainlineBradley Smith2016-01-151-0/+25
| | | | llvm-svn: 257884
* [mips] Never select JAL for calls to an absolute immediate address.Daniel Sanders2016-01-113-0/+3
| | | | | | | | | | | | | | | Summary: It actually takes an offset into the current PC-region. This fixes the 'expr' command in lldb. Reviewers: vkalintiris, jaydeep, bhushan Subscribers: dsanders, llvm-commits Differential Revision: http://reviews.llvm.org/D16054 llvm-svn: 257339
* [AVX-512] Fix test case update missed in r257299.Craig Topper2016-01-111-1/+1
| | | | llvm-svn: 257303
* Fix several accidental DOS line endings in source filesDimitry Andric2016-01-031-42/+42
| | | | | | | | | | | | | | | Summary: There are a number of files in the tree which have been accidentally checked in with DOS line endings. Convert these to native line endings. There are also a few files which have DOS line endings on purpose, and I have set the svn:eol-style property to 'CRLF' on those. Reviewers: joerg, aaron.ballman Subscribers: aaron.ballman, sanjoy, dsanders, llvm-commits Differential Revision: http://reviews.llvm.org/D15848 llvm-svn: 256707
* [mips][microMIPS] Implement DERET and DI instructions and check size operand ↵Zlatko Buljan2015-12-212-0/+6
| | | | | | | | for EXT and DEXT* instructions Differential Revision: http://reviews.llvm.org/D15570 llvm-svn: 256152
* [mips][microMIPS][DSP] Implement PACKRL.PH, PICK.PH, PICK.QB, SHILO, SHILOV ↵Zlatko Buljan2015-12-183-0/+17
| | | | | | | | and WRDSP instructions Differential Revision: http://reviews.llvm.org/D14429 llvm-svn: 255991
* Revert "[ARM] Add ARMv8.2-A FP16 scalar instructions"Reid Kleckner2015-12-164-746/+0
| | | | | | This reverts commit r255762. llvm-svn: 255806
* [ARM] Add ARMv8.2-A FP16 vector instructionsOliver Stannard2015-12-164-0/+1166
| | | | | | | | | | | | | | ARMv8.2-A adds 16-bit floating point versions of all existing SIMD floating-point instructions. This is an optional extension, so all of these instructions require the FeatureFullFP16 subtarget feature. Note that VFP without SIMD is not a valid combination for any version of ARMv8-A, but I have ensured that these instructions all depend on both FeatureNEON and FeatureFullFP16 for consistency. Differential Revision: http://reviews.llvm.org/D15039 llvm-svn: 255764
* [ARM] Add ARMv8.2-A FP16 scalar instructionsOliver Stannard2015-12-164-0/+746
| | | | | | | | | | | | | | | | | | | | | | | | | | | ARMv8.2-A adds 16-bit floating point versions of all existing VFP floating-point instructions. This is an optional extension, so all of these instructions require the FeatureFullFP16 subtarget feature. The assembly for these instructions uses S registers (AArch32 does not have H registers), but the instructions have ".f16" type specifiers rather than ".f32" or ".f64". The top 16 bits of each source register are ignored, and the top 16 bits of the destination register are set to zero. These instructions are mostly the same as the 32- and 64-bit versions, but they use coprocessor 9 rather than 10 and 11. Two new instructions, VMOVX and VINS, have been added to allow packing and extracting two 16-bit floats stored in the top and bottom halves of an S register. New fixup kinds have been added for the PC-relative load and store instructions, but no ELF relocations have been added as they have a range of 512 bytes. Differential Revision: http://reviews.llvm.org/D15038 llvm-svn: 255762
* Revert r254897 "[mips][microMIPS] Implement LH, LHE, LHU and LHUE instructions"Zlatko Buljan2015-12-092-8/+0
| | | | | | | | | Commited patch was intended to implement LH, LHE, LHU and LHUE instructions. After commit test-suite failed with error message in the form of: fatal error: error in backend: Cannot select: t124: i32,ch = load<LD2[%d](tbaa=<0x94acc48>), sext from i16> t0, t2, undef:i32 For that reason I decided to revert commit r254897 and make new patch which besides implementation and standard regression tests will also have dedicated tests (CodeGen) for the above error. llvm-svn: 255109
* [AArch64] Add ARMv8.2-A FP16 vector instructionsOliver Stannard2015-12-081-0/+382
| | | | | | | | | | | | | | | | | ARMv8.2-A adds 16-bit floating point versions of all existing SIMD floating-point instructions. This is an optional extension, so all of these instructions require the FeatureFullFP16 subtarget feature. Note that VFP without SIMD is not a valid combination for any version of ARMv8-A, but I have ensured that these instructions all depend on both FeatureNEON and FeatureFullFP16 for consistency. The ".2h" vector type specifier is now legal (for the scalar pairwise reduction instructions), so some unrelated tests have been modified as different error messages are emitted. This is not a problem as the invalid operands are still caught. llvm-svn: 255010
* [mips][microMIPS] Implement LH, LHE, LHU and LHUE instructionsZlatko Buljan2015-12-072-0/+8
| | | | | | Differential Revision: http://reviews.llvm.org/D9824 llvm-svn: 254897
* [AArch64] Clean up statistical profiling testOliver Stannard2015-12-041-4/+0
| | | | | | | This check has nothing to do with the statistical profiling extension, so shouldn't be in this test. llvm-svn: 254709
* [mips][DSP] Add DSPr1 and DSPr2 tests for the standard encodingsZlatko Buljan2015-12-032-0/+298
| | | | | | Differential Revision: http://reviews.llvm.org/D15141 llvm-svn: 254598
* [mips][microMIPS] Implement PREPEND, RADDU.W.QB, RDDSP, REPL.PH, REPL.QB, ↵Hrvoje Varga2015-12-022-0/+8
| | | | | | | | REPLV.PH, REPLV.QB and MTHLIP instructions Differential Revision: http://reviews.llvm.org/D14527 llvm-svn: 254496
* [mips][microMIPS] Implement RECIP.fmt, RINT.fmt, ROUND.L.fmt, ROUND.W.fmt, ↵Hrvoje Varga2015-12-012-0/+32
| | | | | | | | SEL.fmt, SELEQZ.fmt, SELNEQZ.fmt and CLASS.fmt Differential Revision: http://reviews.llvm.org/D13885 llvm-svn: 254405
* [AArch64] Add ARMv8.2-A Statistical Profiling ExtensionOliver Stannard2015-12-011-0/+91
| | | | | | | | | | | | The Statistical Profiling Extension is an optional extension to ARMv8.2-A. Since it is an optional extension, I have added the FeatureSPE subtarget feature to control it. The assembler-visible parts of this extension are the new "psb csync" instruction, which is equivalent to "hint #17", and a number of system registers. Differential Revision: http://reviews.llvm.org/D15021 llvm-svn: 254401
* [mips][microMIPS] Implement LBUX, LHX, LWX, MAQ_S[A].W.PHL, MAQ_S[A].W.PHR, ↵Hrvoje Varga2015-11-301-0/+11
| | | | | | | | MFHI, MFLO, MTHI and MTLO instructions Differential Revision: http://reviews.llvm.org/D14436 llvm-svn: 254297
* [mips][microMIPS] Fix issue with offset operand of BALC and BC instructionsZoran Jovanovic2015-11-301-2/+2
| | | | | | | Value of offset operand for microMIPS BALC and BC instructions is currently shifted 2 bits, but it should be 1 bit. Differential Revision: http://reviews.llvm.org/D14770 llvm-svn: 254296
* [mips][microMIPS] Implement PRECR.QB.PH, PRECR_SRA[_R].PH.W, PRECRQ.PH.W, ↵Zlatko Buljan2015-11-302-0/+11
| | | | | | | | PRECRQ.QB.PH, PRECRQU_S.QB.PH and PRECRQ_RS.PH.W instructions Differential Revision: http://reviews.llvm.org/D14605 llvm-svn: 254291
* [AArch64] Add ARMv8.2-A FP16 scalar instructionsOliver Stannard2015-11-273-0/+326
| | | | | | | | | | | | | | | ARMv8.2-A adds 16-bit floating point versions of all existing VFP floating-point instructions. This is an optional extension, so all of these instructions require the FeatureFullFP16 subtarget feature. Most of these instructions are the same as the 32- and 64-bit versions, but with the type field (bits 23-22) set to 0b11. Previously the top bit of the size field was always 0, so the instruction classes only provided a 1-bit size field, which I have widened to 2 bits. Differential Revision: http://reviews.llvm.org/D15014 llvm-svn: 254198
* [AArch64] Add ARMv8.2-A new AT instruction variantsOliver Stannard2015-11-261-0/+9
| | | | | | | | | | | ARMv8.2-A adds new variants of the "at" (address translate) system instruction, which take the PSTATE.PAN bit (added in ARMv8.1-A). These are a required part of ARMv8.2-A, so no additional subtarget features are required. Differential Revision: http://reviews.llvm.org/D15018 llvm-svn: 254159
* [AArch64] Add ARMv8.2-A UAO PSTATE bitOliver Stannard2015-11-261-0/+19
| | | | | | | | | | | | | ARMv8.2-A adds a new PSTATE bit, PSTATE.UAO, which allows the LDTR/STTR instructions to behave the same as LDR/STR with respect to execute-only pages at higher privilege levels. New variants of the MSR/MRS instructions are added to allow reading and writing this bit. It is a required part of ARMv8.2-A, so no additional subtarget features are required. Differential Revision: http://reviews.llvm.org/D15020 llvm-svn: 254157
* [AArch64] Add ARMv8.2-A persistent memory instructionOliver Stannard2015-11-261-0/+6
| | | | | | | | | | | ARMv8.2-A adds the "dc cvap" instruction, which is a system instruction that cleans caches to the point of persistence (for systems that have persistent memory). It is a required part of ARMv8.2-A, so no additional subtarget features are required. Differential Revision: http://reviews.llvm.org/D15016 llvm-svn: 254156
* [AArch64] Add ARMv8.2-A ID_A64MMFR2_EL1 registerOliver Stannard2015-11-261-0/+4
| | | | | | | | | | ARMv8.2-A adds a new ID register, ID_A64MMFR2_EL1, which behaves in the same way as ID_A64MMFR0_EL1 and ID_A64MMFR1_EL1. It is a required part of ARMv8.2-A, so no additional subtarget features are required. Differential Revision: http://reviews.llvm.org/D15017 llvm-svn: 254155
* [mips][microMIPS] Implement MUL[_S].PH, MULEQ_S.W.PHL, MULEQ_S.W.PHR, ↵Hrvoje Varga2015-11-202-0/+15
| | | | | | | | MULEU_S.PH.QBL, MULEU_S.PH.QBR, MULQ_RS.PH, MULQ_RS.W, MULQ_S.PH and MULQ_S.W instructions Differential Revision: http://reviews.llvm.org/D14280 llvm-svn: 253651
* [mips][microMIPS] Implement DPS.W.PH, DPSQ_S.W.PH, DPSQ_SA.L.W, ↵Hrvoje Varga2015-11-182-0/+12
| | | | | | | | DPSQX_S.W.PH, DPSQX_SA.W.PH, DPSU.H.QBL, DPSU.H.QBR and DPSX.W.PH instructions Differential Revision: http://reviews.llvm.org/D14058 llvm-svn: 253443
* [mips][microMIPS] Implement EXTP, EXTPDP, EXTPDPV, EXTPV, EXTR[_RS].W, ↵Zlatko Buljan2015-11-172-0/+24
| | | | | | | | EXTR_S.H, EXTRV[_RS].W and EXTRV_S.H instructions Differential Revision: http://reviews.llvm.org/D14174 llvm-svn: 253332
* [mips][microMIPS] Implement SUBQ[_S].PH, SUBQ_S.W, SUBQH[_R].PH, ↵Zlatko Buljan2015-11-172-0/+18
| | | | | | | | SUBQH[_R].W, SUBU[_S].PH, SUBU[_S].QB and SUBUH[_R].QB instructions Differential Revision: http://reviews.llvm.org/D14114 llvm-svn: 253329
* [mips][microMIPS] Implement PRECEQ.W.PHL, PRECEQ.W.PHR, PRECEQU.PH.QBL, ↵Zlatko Buljan2015-11-172-0/+20
| | | | | | | | PRECEQU.PH.QBLA, PRECEQU.PH.QBR, PRECEQU.PH.QBRA, PRECEU.PH.QBL, PRECEU.PH.QBLA, PRECEU.PH.QBR and PRECEU.PH.QBRA instructions Differential Revision: http://reviews.llvm.org/D14279 llvm-svn: 253326
* Added microMIPSDSPr1 assembler and disassembler tests to existing ↵Zlatko Buljan2015-11-172-7/+43
| | | | | | microMIPSDSPr2 test files. llvm-svn: 253320
* [mips][microMIPS] Implement SHRA[_R].PH, SHRAV[_R].PH, SHRAV[_R].QB, ↵Zlatko Buljan2015-11-132-0/+12
| | | | | | | | SHRAV_R.W, SHRA_R.W, SHRL.PH, SHRL.QB, SHRLV.PH and SHRLV.QB instructions Differential Revision: http://reviews.llvm.org/D14010 llvm-svn: 253041
* [mips][microMIPS] Implement LWM16, SB16, SH16, SW16, SWSP and SWM16 instructionsZlatko Buljan2015-11-122-0/+14
| | | | | | Differential Revision: http://reviews.llvm.org/D11406 llvm-svn: 252885
* [Hexagon] Fixing store instructions and reenabling a few more tests.Colin LeMahieu2015-11-101-1/+0
| | | | llvm-svn: 252561
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