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path: root/llvm/test/MC/Disassembler/X86/intel-syntax.txt
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* [X86] Don't print 'dword ptr' or 'qword ptr' on the operand to some of the ↵Craig Topper2015-01-081-0/+20
| | | | | | LEA variants in Intel syntax. The memory operand is inherently unsized. llvm-svn: 225432
* Fixing Intel format of the vshufpd instruction.Yunzhong Gao2013-09-271-0/+3
| | | | | | Phabricator code review is located at: http://llvm-reviews.chandlerc.com/D1759 llvm-svn: 191481
* First round of fixes for the x86 fixes for the x86 move accumulator from/to ↵Craig Topper2013-08-251-0/+30
| | | | | | | | | | | | | | memory offset instructions. -Assembly parser now properly check the size of the memory operation specified in intel syntax. So 'mov word ptr [5], al' is no longer accepted. -x86-32 disassembly of these instructions no longer sign extends the 32-bit address immediate based on size. -Intel syntax printing prints the ptr size and places brackets around the address immediate. Known remaining issues with these instructions: -Segment override prefix is not supported. PR16962 and PR16961. -Immediate size should be changed by address size prefix. llvm-svn: 189201
* Changed register names (and pointer keywords) to be lower case when using ↵Craig Topper2013-07-311-26/+26
| | | | | | | | Intel X86 assembler syntax. Patch by Richard Mitton. llvm-svn: 187476
* fixed xsave, xsaveopt, xrstor mnemonics with intel syntax; added test casesKay Tiong Khoo2013-04-101-0/+9
| | | | llvm-svn: 179223
* Make x86 asm parser to check for xmm vs ymm for index register in gather ↵Craig Topper2012-07-181-0/+5
| | | | | | instructions. Also fix Intel syntax for gather instructions to use 'DWORD PTR' or 'QWORD PTR' to match gas. llvm-svn: 160420
* Add -disassemble support for -show-inst and -show-encode capability llvm-mc. ↵Richard Barton2012-04-161-1/+1
| | | | | | | | Also refactor so all MC paraphernalia are created once for all uses as much as possible. The test change is to account for the fact that the default disassembler behaviour has changed with regards to specifying the assembly syntax to use. llvm-svn: 154809
* Add retw and lretw instructions. Also, fix Intel syntax parsing for allCharles Davis2012-04-111-0/+6
| | | | | | ret instructions. llvm-svn: 154468
* Fix disasm of iret, sysexit, and sysret when displayed with Intel syntax.Bill Wendling2012-03-101-0/+22
| | | | | | Patch by Kay Tiong Khoo! llvm-svn: 152487
* Fix some Intel syntax disassembly issues with instructions that implicitly ↵Craig Topper2011-10-021-0/+57
| | | | | | use AL/AX/EAX/RAX such as ADD/SUB/ADC/SUBB/XOR/OR/AND/CMP/MOV/TEST. llvm-svn: 140974
* Don't allow 32-bit only instructions to be disassembled in 64-bit mode. ↵Craig Topper2011-09-231-7/+4
| | | | | | Fixes part of PR10700. llvm-svn: 140370
* Fix register printing in disassembling of push/pop of segment registers and ↵Craig Topper2011-09-221-0/+12
| | | | | | in/out in Intel syntax mode. Fixes PR10960 llvm-svn: 140299
* Add disassembler test for Intel syntax. Tests r139353.Craig Topper2011-09-091-0/+13
llvm-svn: 139356
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