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* [PowerPC] Enable printing instructions using aliasesHal Finkel2015-04-231-427/+427
| | | | | | | | | | | TableGen had been nicely generating code to print a number of instructions using shorter aliases (and PowerPC has plenty of short mnemonics), but we were not calling it. For some of the aliases we support in the parser, TableGen can't infer the "inverse" alias relationship, so there is still more to do. Thus, after some hours of updating test cases... llvm-svn: 235616
* [PowerPC] Add asm support for cache-inhibited ld/st instructionsHal Finkel2014-11-301-0/+17
| | | | | | | | | Add assembler support for the fixed-point cache-inhibited load/store instructions. These are hypervisor-level only, so don't get too excited ;) Fixes PR21650. llvm-svn: 222976
* [PowerPC] Add the 'attn' instructionHal Finkel2014-11-251-0/+4
| | | | | | | | The attn instruction is not part of the Power ISA, but is documented in the A2 user manual, and is accepted by the GNU assembler for the A2 and the POWER4+. Reported as part of PR21650. llvm-svn: 222712
* Add RFID instruction.Joerg Sonnenberger2014-08-071-0/+3
| | | | llvm-svn: 215105
* Add lswi / stswi for assembler use with a warning to not add patternsJoerg Sonnenberger2014-08-051-0/+5
| | | | | | for them. llvm-svn: 214862
* Add features for PPC 4xx and e500/e500mc instructions.Joerg Sonnenberger2014-08-041-10/+0
| | | | | | Move the test cases for them into separate files. llvm-svn: 214724
* tlbia supportJoerg Sonnenberger2014-08-021-0/+3
| | | | llvm-svn: 214640
* mfdcr / mtdcr supportJoerg Sonnenberger2014-08-021-0/+5
| | | | llvm-svn: 214639
* Don't use additional arguments for dss and friends to satisfy DSS_Form,Joerg Sonnenberger2014-08-021-0/+13
| | | | | | | | | when let can do the same thing. Keep the 64bit variants as codegen-only. While they have a different register class, the encoding is the same for 32bit and 64bit mode. Having both present would otherwise confuse the disassembler. llvm-svn: 214636
* Add rfdi and rfmci from the e500/e500mc ISA.Joerg Sonnenberger2014-07-301-0/+4
| | | | llvm-svn: 214339
* Add a disassembler to the PowerPC backendHal Finkel2013-12-191-0/+2253
The tests for the disassembler were adapted from the encoder tests, and for the most part, the output from the disassembler matches that encoder-test inputs. There are some places where more-informative mnemonics could be produced (notably for the branch instructions), and those cases are noted in the tests with FIXMEs. Future work includes: - Generating more-informative mnemonics when possible (this may also be done in the printer). - Remove the dependence on positional "numbered" operand-to-variable mapping (for both encoding and decoding). - Internally using 64-bit instruction variants in 64-bit mode (if this turns out to matter). llvm-svn: 197693
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