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* [mips] Attempt to fix llvm-s390x-linux1Daniel Sanders2015-09-111-1/+1
| | | | | | It doesn't seem to like the '|&' in the test command. llvm-svn: 247418
* [mips] Add missing MIPS-IV disassembler tests.Daniel Sanders2015-09-113-0/+54
| | | | llvm-svn: 247417
* [mips] Add missing MIPS-III disassembler tests.Daniel Sanders2015-09-113-0/+48
| | | | llvm-svn: 247416
* [mips] Add missing MIPS-II disassembler tests.Daniel Sanders2015-09-113-0/+44
| | | | | | | These tests were found by llvm-mc-fuzzer (see http://reviews.llvm.org/D12723) and were verified by checking the disassembler output is accepted by GAS. llvm-svn: 247414
* Re-commit r247405: [mips] Add missing MIPS-I disassembler tests.Daniel Sanders2015-09-114-0/+67
| | | | | | | | | | | | | These tests were found by llvm-mc-fuzzer (see http://reviews.llvm.org/D12723) and verified by checking the disassembler output is accepted by GAS. The problematic tests from the previous commit have been moved to valid-xfail.txt for now. Also, give invalid instructions some coverage. invalid-xfail.txt contains instructions that should be invalid but successfully disassemble. llvm-svn: 247407
* Revert r247405: [mips] Add missing MIPS-I disassembler tests.Daniel Sanders2015-09-111-29/+0
| | | | | | A small number of the added tests have operands that change on each round trip. llvm-svn: 247406
* [mips] Add missing MIPS-I disassembler tests.Daniel Sanders2015-09-111-0/+29
| | | | | | | These tests were found by llvm-mc-fuzzer (see http://reviews.llvm.org/D12723) and verified by checking the disassembler output is accepted by GAS. llvm-svn: 247405
* [mips][microMIPS] Implement ADDU16, AND16, ANDI16, NOT16, OR16, SLL16 and ↵Zoran Jovanovic2015-09-091-0/+14
| | | | | | | | SRL16 instructions Differential Revision: http://reviews.llvm.org/D11178 llvm-svn: 247146
* [mips][microMIPS] Implement CACHEE and PREFE instructionsZoran Jovanovic2015-09-092-0/+8
| | | | | | Differential Revision: http://reviews.llvm.org/D11628 llvm-svn: 247125
* [mips][microMIPS] Implement LLE, LUI, LW and LWE instructionsZoran Jovanovic2015-09-081-0/+8
| | | | | | Differential Revision: http://reviews.llvm.org/D1179 llvm-svn: 247017
* [mips][microMIPS] Implement SB, SBE, SCE, SH and SHE instructionsZoran Jovanovic2015-09-081-0/+10
| | | | | | Differential Revision: http://reviews.llvm.org/D11801 llvm-svn: 246999
* [mips][microMIPS] Add microMIPS32r6 and microMIPS64r6 tests for existing ↵Zoran Jovanovic2015-09-082-0/+24
| | | | | | | | 16-bit LBU16, LHU16, LW16, LWGP and LWSP instructions Differential Revision: http://reviews.llvm.org/D10956 llvm-svn: 246987
* [mips][microMIPS] Implement ABS.fmt, CEIL.L.fmt, CEIL.W.fmt, FLOOR.L.fmt, ↵Zoran Jovanovic2015-09-072-0/+72
| | | | | | | | FLOOR.W.fmt, TRUNC.L.fmt, TRUNC.W.fmt, RSQRT.fmt and SQRT.fmt instructions Differential Revision: http://reviews.llvm.org/D11674 llvm-svn: 246968
* [mips][microMIPS] Implement BC16, BEQZC16 and BNEZC16 instructionsZoran Jovanovic2015-09-072-0/+12
| | | | | | Differential Revision: http://reviews.llvm.org/D11181 llvm-svn: 246963
* [mips][microMIPS] Implement CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, ↵Zoran Jovanovic2015-09-072-0/+200
| | | | | | | | MAX.fmt, MIN.fmt, MAXA.fmt, MINA.fmt and CMP.condn.fmt instructions Differential Revision: http://reviews.llvm.org/D12141 llvm-svn: 246960
* [mips][microMIPS] Implement ADD.fmt, SUB.fmt, MOV.fmt, MUL.fmt, DIV.fmt, ↵Zoran Jovanovic2015-09-052-0/+64
| | | | | | | | MADDF.fmt, MSUBF.fmt and NEG.fmt instructions Differential Revision: http://reviews.llvm.org/D11978 llvm-svn: 246919
* [mips][microMIPS] Add microMIPS32r6 and microMIPS64r6 tests for existing ↵Zoran Jovanovic2015-08-202-0/+36
| | | | | | | | 16-bit ADDIUR1SP, ADDIUR2, ADDIUS5 and ADDIUSP instructions Differential Revision: http://reviews.llvm.org/D10955 llvm-svn: 245554
* [mips][microMIPS] Implement DDIV, DMOD, DDIVU and DMODU instructionsZoran Jovanovic2015-08-181-0/+8
| | | | | | Differential Revision: http://reviews.llvm.org/D10953 llvm-svn: 245297
* [mips][microMIPS] Implement SW and SWE instructionsZoran Jovanovic2015-08-181-0/+3
| | | | | | Differential Revision: http://reviews.llvm.org/D10869 llvm-svn: 245293
* [mips][microMIPS] Create microMIPS64r6 subtarget and implement DALIGN, DAUI, ↵Zoran Jovanovic2015-08-121-0/+15
| | | | | | | | DAHI, DATI, DEXT, DEXTM and DEXTU instructions Differential Revision: http://reviews.llvm.org/D10923 llvm-svn: 244744
* [mips] Remap move as or.Vasileios Kalintiris2015-08-1122-1/+47
| | | | | | | | | | | | | | | | | | | | | | | | Summary: This patch remaps the assembly idiom 'move' to 'or' instead of 'daddu' or 'addu'. The use of addu/daddu instead of or as move was highlighted as a performance issue during the analysis of a recent 64bit design. Originally move was encoded as 'or' by binutils but was changed for the r10k cpu family due to their pipeline which had 2 arithmetic units and a single logical unit, and so could issue multiple (d)addu based moves at the same time but only 1 logical move. This patch preserves the disassembly behaviour so that disassembling a old style (d)addu move still appears as move, but assembling move always gives an or Patch by Simon Dardis. Reviewers: vkalintiris Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D11796 llvm-svn: 244579
* [mips] Added support for the ERETNC instruction.Vasileios Kalintiris2015-07-204-0/+4
| | | | | | | | | | | | | | Summary: This required adding the instruction predicate HasMips32r5. Patch by Scott Egerton. Reviewers: dsanders, vkalintiris Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D11136 llvm-svn: 242666
* [mips][microMIPS] Implement SLL and NOP instructionsZoran Jovanovic2015-07-011-0/+4
| | | | | | http://reviews.llvm.org/D10474 llvm-svn: 241150
* [mips] Fold duplicate big-endian disassembler tests together.Daniel Sanders2015-06-2714-1398/+122
| | | | llvm-svn: 240887
* [mips] Sort big-endian disassembler tests by opcode.Daniel Sanders2015-06-2714-2205/+2193
| | | | llvm-svn: 240885
* [mips] Make little-endian disassembler test filenames consistent.Daniel Sanders2015-06-273-0/+0
| | | | | | Most are named *-el.txt. Renamed the three that were *-le.txt llvm-svn: 240884
* [mips] Add COP0 register class and use it in M[FT]C0/DM[FT]C0.Daniel Sanders2015-06-2726-0/+98
| | | | | | | | | | | | | | | | | Summary: Previously it (incorrectly) used GPR's. Patch by Simon Dardis. A couple small corrections by myself. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D10567 llvm-svn: 240883
* [mips][microMIPS] Implement BREAK, EHB and EI instructionsZoran Jovanovic2015-06-243-0/+20
| | | | | | http://reviews.llvm.org/D10090 llvm-svn: 240531
* [mips][microMIPS] Implement ERET and ERETNC instructionsZoran Jovanovic2015-06-111-10/+9
| | | | | | http://reviews.llvm.org/D10091 llvm-svn: 239522
* [mips][microMIPSr6] Change disassembler tests to one line formatZoran Jovanovic2015-06-112-672/+336
| | | | llvm-svn: 239519
* [mips][microMIPSr6] Implement SEB and SEH instructionsZoran Jovanovic2015-05-271-0/+4
| | | | | | Differential Revision: http://reviews.llvm.org/D9739 llvm-svn: 238333
* [mips][microMIPSr6] Implement BEQZALC, BGEZALC, BGTZALC, BLEZALC, BLTZALC ↵Jozef Kolek2015-05-271-0/+12
| | | | | | | | | | | and BNEZALC instructions This patch implements microMIPS32r6 BEQZALC, BGEZALC, BGTZALC, BLEZALC, BLTZALC and BNEZALC instructions using mapping. Differential Revision: http://reviews.llvm.org/D10031 llvm-svn: 238325
* [mips][microMIPSr6] Implement NOR, OR, ORI, XOR and XORI instructionsZoran Jovanovic2015-05-191-0/+10
| | | | | | Differential Revision: http://reviews.llvm.org/D8800 llvm-svn: 237697
* [mips][microMIPSr6] Implement AND and ANDI instructionsZoran Jovanovic2015-05-191-0/+4
| | | | | | Differential Revision: http://reviews.llvm.org/D8772 llvm-svn: 237696
* [mips][microMIPSr6] Implement DIV, DIVU, MOD and MODU instructionsZoran Jovanovic2015-05-191-0/+8
| | | | | | Differential Revision: http://reviews.llvm.org/D8769 llvm-svn: 237685
* [mips][microMIPSr6] Implement LSA instructionJozef Kolek2015-05-181-0/+2
| | | | | | | | This patch implements LSA instruction using mapping. Differential Revision: http://reviews.llvm.org/D8919 llvm-svn: 237634
* [mips][microMIPSr6] Implement ALIGN and AUI instructionsJozef Kolek2015-05-181-0/+4
| | | | | | | | This patch implements ALIGN and AUI instructions using mapping. Differential Revision: http://reviews.llvm.org/D8782 llvm-svn: 237563
* [mips][microMIPSr6] Implement CLO and CLZ instructionsJozef Kolek2015-05-131-0/+4
| | | | | | | | This patch implements CLO and CLZ instructions using mapping. Differential Revision: http://reviews.llvm.org/D8553 llvm-svn: 237257
* [mips][microMIPSr6] Implement SELEQZ and SELNEZ instructionsJozef Kolek2015-05-121-0/+4
| | | | | | | | This patch implements SELEQZ and SELNEZ instructions using mapping. Differential Revision: http://reviews.llvm.org/D8497 llvm-svn: 237158
* [mips][microMIPSr6] Implement ALUIPC and AUIPC instructionsJozef Kolek2015-05-081-0/+4
| | | | | | | | This patch implements ALUIPC and AUIPC instructions using mapping. Differential Revision: http://reviews.llvm.org/D8441 llvm-svn: 236858
* [mips][microMIPSr6] Implement ADDIUPC and LWPC instructionsJozef Kolek2015-05-081-0/+4
| | | | | | | | This patch implements ADDIUPC and LWPC instructions using mapping. Differential Revision: http://reviews.llvm.org/D8415 llvm-svn: 236852
* [mips][microMIPSr6] Implement JIALC and JIC instructionsJozef Kolek2015-05-071-0/+4
| | | | | | | | This patch implements JIALC and JIC instructions using mapping. Differential Revision: http://reviews.llvm.org/D8389 llvm-svn: 236748
* [mips][msa] Test basic operations for the N32 ABI too.Daniel Sanders2015-05-057-0/+14
| | | | | | | | | | | | | | | | | Summary: This required adding instruction aliases for dneg. N64 will be enabled shortly but requires additional bugfixes. Reviewers: vkalintiris Reviewed By: vkalintiris Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D9341 llvm-svn: 236489
* [mips] Sorted instructions in mips64r6 disassembly tests. NFC.Daniel Sanders2015-04-302-186/+186
| | | | llvm-svn: 236223
* [mips][microMIPSr6] Implement MUL, MUH, MULU and MUHU instructionsZoran Jovanovic2015-04-291-0/+8
| | | | | | Differential Revision: http://reviews.llvm.org/D8894 llvm-svn: 236131
* [mips][microMIPSr6] Implement SUB and SUBU instructionsZoran Jovanovic2015-04-291-0/+5
| | | | | | Differential Revision: http://reviews.llvm.org/D8764 llvm-svn: 236118
* [mips][microMIPSr6] Implement ADD, ADDU and ADDIU instructionsZoran Jovanovic2015-04-291-0/+6
| | | | | | Differential Revision: http://reviews.llvm.org/D8704 llvm-svn: 236111
* [mips][microMIPSr6] Implement CACHE and PREF instructionsJozef Kolek2015-04-211-0/+6
| | | | | | | | Implement CACHE and PREF instructions using mapping. Differential Revision: http://reviews.llvm.org/D8893 llvm-svn: 235379
* [mips][microMIPSr6] Implement BITSWAP instructionJozef Kolek2015-04-201-0/+3
| | | | | | | | Implement BITSWAP instruction using mapping. Differential Revision: http://reviews.llvm.org/D8857 llvm-svn: 235321
* [mips][microMIPSr6] Implement disassembler supportJozef Kolek2015-04-201-0/+7
| | | | | | | | Implement disassembler support for microMIPS32r6. Differential Revision: http://reviews.llvm.org/D8490 llvm-svn: 235307
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