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* [mips] Range check uimm20 and fixed a bug this revealed.Daniel Sanders2016-02-291-3/+3
| | | | | | | | | | | | | | | | | | | Summary: The bug was that dextu's operand 3 would print 0-31 instead of 32-63 when printing assembly. This came up when replacing MipsInstPrinter::printUnsignedImm() with a version that could handle arbitrary bit widths. MipsAsmPrinter::printUnsignedImm*() don't seem to be used so they have been removed. Reviewers: vkalintiris Subscribers: dsanders, llvm-commits Differential Revision: http://reviews.llvm.org/D15521 llvm-svn: 262231
* [mips][microMIPS] Implement DINSU, DINSM, DINS instructionsHrvoje Varga2016-02-251-0/+3
| | | | | | Differential Revision: http://reviews.llvm.org/D16181 llvm-svn: 261860
* [mips][microMIPS] Implement TLBINV and TLBINVF instructionsZlatko Buljan2016-02-182-0/+4
| | | | | | Differential Revision: http://reviews.llvm.org/D16849 llvm-svn: 261211
* [mips] Range check uimm16 and fix several bugs this revealed.Daniel Sanders2016-02-0114-70/+70
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: The bugs were: * teq and similar take 4-bit unsigned immediates on microMIPS. * teqi and similar have side-effects like teq do. * shll_s.w and shra_r.w take 5-bit unsigned immediates. * The various DSP ext* instructions take a 5-bit immediate. * repl.qh takes an 8-bit unsigned immediate. * repl.ph takes a 10-bit unsigned immediate. * rddsp/wrdsp take a 10-bit unsigned immediate. * teqi and similar take signed 16-bit immediates (10-bit for microMIPS). * Out-of-range immediate macros for or/xor take a simm32/simm64 depending on architecture. I'll fix the simm64 case properly when I reach simm32. lui is a bit more lenient than GAS and accepts signed immediates in addition to unsigned. This is because MipsMCExpr can produce signed values when constant folding and it currently lacks a way of knowing it should fold to an unsigned value. Reviewers: vkalintiris Subscribers: dsanders, llvm-commits Differential Revision: http://reviews.llvm.org/D15446 llvm-svn: 259360
* [mips] Never select JAL for calls to an absolute immediate address.Daniel Sanders2016-01-113-0/+3
| | | | | | | | | | | | | | | Summary: It actually takes an offset into the current PC-region. This fixes the 'expr' command in lldb. Reviewers: vkalintiris, jaydeep, bhushan Subscribers: dsanders, llvm-commits Differential Revision: http://reviews.llvm.org/D16054 llvm-svn: 257339
* Fix several accidental DOS line endings in source filesDimitry Andric2016-01-031-42/+42
| | | | | | | | | | | | | | | Summary: There are a number of files in the tree which have been accidentally checked in with DOS line endings. Convert these to native line endings. There are also a few files which have DOS line endings on purpose, and I have set the svn:eol-style property to 'CRLF' on those. Reviewers: joerg, aaron.ballman Subscribers: aaron.ballman, sanjoy, dsanders, llvm-commits Differential Revision: http://reviews.llvm.org/D15848 llvm-svn: 256707
* [mips][microMIPS] Implement DERET and DI instructions and check size operand ↵Zlatko Buljan2015-12-212-0/+6
| | | | | | | | for EXT and DEXT* instructions Differential Revision: http://reviews.llvm.org/D15570 llvm-svn: 256152
* [mips][microMIPS][DSP] Implement PACKRL.PH, PICK.PH, PICK.QB, SHILO, SHILOV ↵Zlatko Buljan2015-12-183-0/+17
| | | | | | | | and WRDSP instructions Differential Revision: http://reviews.llvm.org/D14429 llvm-svn: 255991
* Revert r254897 "[mips][microMIPS] Implement LH, LHE, LHU and LHUE instructions"Zlatko Buljan2015-12-092-8/+0
| | | | | | | | | Commited patch was intended to implement LH, LHE, LHU and LHUE instructions. After commit test-suite failed with error message in the form of: fatal error: error in backend: Cannot select: t124: i32,ch = load<LD2[%d](tbaa=<0x94acc48>), sext from i16> t0, t2, undef:i32 For that reason I decided to revert commit r254897 and make new patch which besides implementation and standard regression tests will also have dedicated tests (CodeGen) for the above error. llvm-svn: 255109
* [mips][microMIPS] Implement LH, LHE, LHU and LHUE instructionsZlatko Buljan2015-12-072-0/+8
| | | | | | Differential Revision: http://reviews.llvm.org/D9824 llvm-svn: 254897
* [mips][DSP] Add DSPr1 and DSPr2 tests for the standard encodingsZlatko Buljan2015-12-032-0/+298
| | | | | | Differential Revision: http://reviews.llvm.org/D15141 llvm-svn: 254598
* [mips][microMIPS] Implement PREPEND, RADDU.W.QB, RDDSP, REPL.PH, REPL.QB, ↵Hrvoje Varga2015-12-022-0/+8
| | | | | | | | REPLV.PH, REPLV.QB and MTHLIP instructions Differential Revision: http://reviews.llvm.org/D14527 llvm-svn: 254496
* [mips][microMIPS] Implement RECIP.fmt, RINT.fmt, ROUND.L.fmt, ROUND.W.fmt, ↵Hrvoje Varga2015-12-012-0/+32
| | | | | | | | SEL.fmt, SELEQZ.fmt, SELNEQZ.fmt and CLASS.fmt Differential Revision: http://reviews.llvm.org/D13885 llvm-svn: 254405
* [mips][microMIPS] Implement LBUX, LHX, LWX, MAQ_S[A].W.PHL, MAQ_S[A].W.PHR, ↵Hrvoje Varga2015-11-301-0/+11
| | | | | | | | MFHI, MFLO, MTHI and MTLO instructions Differential Revision: http://reviews.llvm.org/D14436 llvm-svn: 254297
* [mips][microMIPS] Fix issue with offset operand of BALC and BC instructionsZoran Jovanovic2015-11-301-2/+2
| | | | | | | Value of offset operand for microMIPS BALC and BC instructions is currently shifted 2 bits, but it should be 1 bit. Differential Revision: http://reviews.llvm.org/D14770 llvm-svn: 254296
* [mips][microMIPS] Implement PRECR.QB.PH, PRECR_SRA[_R].PH.W, PRECRQ.PH.W, ↵Zlatko Buljan2015-11-302-0/+11
| | | | | | | | PRECRQ.QB.PH, PRECRQU_S.QB.PH and PRECRQ_RS.PH.W instructions Differential Revision: http://reviews.llvm.org/D14605 llvm-svn: 254291
* [mips][microMIPS] Implement MUL[_S].PH, MULEQ_S.W.PHL, MULEQ_S.W.PHR, ↵Hrvoje Varga2015-11-202-0/+15
| | | | | | | | MULEU_S.PH.QBL, MULEU_S.PH.QBR, MULQ_RS.PH, MULQ_RS.W, MULQ_S.PH and MULQ_S.W instructions Differential Revision: http://reviews.llvm.org/D14280 llvm-svn: 253651
* [mips][microMIPS] Implement DPS.W.PH, DPSQ_S.W.PH, DPSQ_SA.L.W, ↵Hrvoje Varga2015-11-182-0/+12
| | | | | | | | DPSQX_S.W.PH, DPSQX_SA.W.PH, DPSU.H.QBL, DPSU.H.QBR and DPSX.W.PH instructions Differential Revision: http://reviews.llvm.org/D14058 llvm-svn: 253443
* [mips][microMIPS] Implement EXTP, EXTPDP, EXTPDPV, EXTPV, EXTR[_RS].W, ↵Zlatko Buljan2015-11-172-0/+24
| | | | | | | | EXTR_S.H, EXTRV[_RS].W and EXTRV_S.H instructions Differential Revision: http://reviews.llvm.org/D14174 llvm-svn: 253332
* [mips][microMIPS] Implement SUBQ[_S].PH, SUBQ_S.W, SUBQH[_R].PH, ↵Zlatko Buljan2015-11-172-0/+18
| | | | | | | | SUBQH[_R].W, SUBU[_S].PH, SUBU[_S].QB and SUBUH[_R].QB instructions Differential Revision: http://reviews.llvm.org/D14114 llvm-svn: 253329
* [mips][microMIPS] Implement PRECEQ.W.PHL, PRECEQ.W.PHR, PRECEQU.PH.QBL, ↵Zlatko Buljan2015-11-172-0/+20
| | | | | | | | PRECEQU.PH.QBLA, PRECEQU.PH.QBR, PRECEQU.PH.QBRA, PRECEU.PH.QBL, PRECEU.PH.QBLA, PRECEU.PH.QBR and PRECEU.PH.QBRA instructions Differential Revision: http://reviews.llvm.org/D14279 llvm-svn: 253326
* Added microMIPSDSPr1 assembler and disassembler tests to existing ↵Zlatko Buljan2015-11-172-7/+43
| | | | | | microMIPSDSPr2 test files. llvm-svn: 253320
* [mips][microMIPS] Implement SHRA[_R].PH, SHRAV[_R].PH, SHRAV[_R].QB, ↵Zlatko Buljan2015-11-132-0/+12
| | | | | | | | SHRAV_R.W, SHRA_R.W, SHRL.PH, SHRL.QB, SHRLV.PH and SHRLV.QB instructions Differential Revision: http://reviews.llvm.org/D14010 llvm-svn: 253041
* [mips][microMIPS] Implement LWM16, SB16, SH16, SW16, SWSP and SWM16 instructionsZlatko Buljan2015-11-122-0/+14
| | | | | | Differential Revision: http://reviews.llvm.org/D11406 llvm-svn: 252885
* [mips][ias] Range check uimm2 operands and fix a bug this revealed.Daniel Sanders2015-11-065-7/+7
| | | | | | | | | | | | | | | Summary: The bug was that the MIPS32R6/MIPS64R6/microMIPS32R6 versions of LSA and DLSA (unlike the MSA version) failed to account for the off-by-one encoding of the immediate. The range is actually 1..4 rather than 0..3. Reviewers: vkalintiris Subscribers: atanasyan, dsanders, llvm-commits Differential Revision: http://reviews.llvm.org/D14015 llvm-svn: 252295
* [mips][microMIPS] Implement PAUSE, RDHWR, RDPGPR, SDBBP, SSNOP, SYNC, SYNCI ↵Hrvoje Varga2015-10-281-0/+12
| | | | | | | | and WAIT instructions Differential Revision: http://reviews.llvm.org/D12628 llvm-svn: 251510
* [mips][microMIPS] Implement SHLL.PH, SHLL_S.PH, SHLL.QB, SHLLV.PH, ↵Zlatko Buljan2015-10-232-0/+10
| | | | | | | | SHLLV_S.PH, SHLLV.QB, SHLLV_S.W, SHLL_S.W, SHRA.QB and SHRA_R.QB instructions Differential Revision: http://reviews.llvm.org/D13929 llvm-svn: 251098
* [mips][msa] Remove copy_u.d and move copy_u.w to MSA64.Daniel Sanders2015-10-212-5/+1
| | | | | | | | | | | | | | | | | | | | | | | Summary: The forwards compatibility strategy employed by MIPS is to consider registers to be infinitely sign-extended. Then on ISA's with a wider register, the result of existing instructions are sign-extended to register width and zero-extended counterparts are added. copy_u.w on MSA32 and copy_u.w on MSA64 violate this strategy and we have therefore corrected the MSA specs to fix this. We still keep track of sign/zero-extension during legalization but we now match copy_s.[wd] where required. No change required to clang since __builtin_msa_copy_u_[wd] will map to copy_s.[wd] where appropriate for the target. Reviewers: vkalintiris Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D13472 llvm-svn: 250887
* [mips][microMIPS] Implement ADDQ.PH, ADDQ_S.W, ADDQH.PH, ADDQH.W, ADDSC, ↵Zlatko Buljan2015-10-192-0/+14
| | | | | | | | ADDU.PH, ADDU_S.QB, ADDWC and ADDUH.QB instructions Differential Revision: http://reviews.llvm.org/D13130 llvm-svn: 250685
* [mips][microMIPS] Implement ABSQ.QB, ABSQ_S.PH, ABSQ_S.W, ABSQ_S.QB, INSV, ↵Zlatko Buljan2015-10-192-1/+11
| | | | | | | | MADD, MADDU, MSUB, MSUBU, MULT and MULTU instructions Differential Revision: http://reviews.llvm.org/D13721 llvm-svn: 250683
* Commited two test files which are forgotten during commit of patch for ↵Zlatko Buljan2015-10-161-0/+6
| | | | | | http://reviews.llvm.org/D13376 llvm-svn: 250512
* [mips][microMIPS] Implement LB, LBE, LBU and LBUE instructionsHrvoje Varga2015-10-161-0/+4
| | | | | | Differential Revision: http://reviews.llvm.org/D11633 llvm-svn: 250511
* [mips][microMIPS] Implement DPA.W.PH, DPAQ_S.W.PH, DPAQ_SA.L.W, ↵Zlatko Buljan2015-10-151-1/+4
| | | | | | | | DPAQX_S.W.PH, DPAQX_SA.W.PH, DPAU.H.QBL, DPAU.H.QBR and DPAX.W.PH instructions Differential Revision: http://reviews.llvm.org/D13376 llvm-svn: 250382
* [mips][microMIPS] Implement BREAK16, LI16, MOVE16, SDBBP16, SUBU16 and XOR16 ↵Hrvoje Varga2015-10-152-0/+31
| | | | | | | | instructions Differential Revision: http://reviews.llvm.org/D11292#inline-103143 llvm-svn: 250381
* [mips][microMIPS] Implement LLE and SCE instructionsHrvoje Varga2015-10-152-0/+4
| | | | | | Differential Revision: http://reviews.llvm.org/D11630 llvm-svn: 250379
* [mips][microMIPS] Implement LWLE, LWRE, SWLE and SWRE instructionsHrvoje Varga2015-10-152-0/+8
| | | | | | Differential Revision: http://reviews.llvm.org/D11631 llvm-svn: 250377
* [mips][micromips] Initial support for micrmomips DSP instructions and ↵Zoran Jovanovic2015-10-121-0/+4
| | | | | | | | addu.qb implementation Differential Revision: http://reviews.llvm.org/D12798 llvm-svn: 250058
* [mips][disassembler] Changed CHECK-EB directives to CHECK so div/divu are ↵Daniel Sanders2015-10-061-2/+2
| | | | | | tested. llvm-svn: 249386
* [mips][disassembler] Merged disassembler tests into the corresponding ↵Daniel Sanders2015-10-0612-1916/+216
| | | | | | ISA/ASE subdirectories. llvm-svn: 249384
* [mips][disassembler] Moved DSP tests into proper place and corrected formatting.Daniel Sanders2015-10-062-22/+9
| | | | llvm-svn: 249383
* [mips][microMIPS] Implement JALRC16, JRCADDIUSP and JRC16 instructionsZoran Jovanovic2015-10-052-0/+12
| | | | | | Differential Revision: http://reviews.llvm.org/D11219 llvm-svn: 249317
* [mips][microMIPS] Implement CACHEE, WRPGPR and WSBH instructionsZoran Jovanovic2015-10-012-0/+10
| | | | | | Differential Revision: http://reviews.llvm.org/D10337 llvm-svn: 249004
* [mips][microMIPS] Fix an invalid read for lwm32 and reserved reglist values.Daniel Sanders2015-09-181-0/+4
| | | | | | | | | | | | | | | Summary: Some values of 'reglist' are reserved and cause the disassembler to read past the end of the Regs array. Treat lwm32's containing reserved values as invalid instructions. Reviewers: zoran.jovanovic Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D12959 llvm-svn: 247990
* [mips][microMIPS] Implement TEQ, TGE, TGEU, TLT, TLTU and TNE instructionsZoran Jovanovic2015-09-174-12/+60
| | | | | | Differential Revision: http://reviews.llvm.org/D9658 llvm-svn: 247880
* [mips][microMIPS] Implement PREFX, LHUE, LBE, LBUE, LHE, LWE, SBE, SHE and ↵Zoran Jovanovic2015-09-162-0/+36
| | | | | | | | SWE instructions Differential Revision: http://reviews.llvm.org/D9189 llvm-svn: 247780
* [mips][microMIPS] Fix an issue with disassembling lwm32 instructionZoran Jovanovic2015-09-152-0/+4
| | | | | | | Fixed microMIPS disassembler crash on test case generated by llvm-mc-fuzzer. Differential Revision: http://reviews.llvm.org/D12881 llvm-svn: 247698
* [mips][microMIPS] Implement CACHEE and PREFE instructions for microMIPS32r6Zoran Jovanovic2015-09-151-0/+4
| | | | | | Differential Revision: http://reviews.llvm.org/D11632 llvm-svn: 247670
* [mips] Added support for various EVA ASE instructions.Daniel Sanders2015-09-152-0/+92
| | | | | | | | | | | | | | | | | | | | Summary: Added support for the following instructions: CACHEE, LBE, LBUE, LHE, LHUE, LWE, LLE, LWLE, LWRE, PREFE, SBE, SHE, SWE, SCE, SWLE, SWRE, TLBINV, TLBINVF This required adding some infrastructure for the EVA ASE. Patch by Scott Egerton. Reviewers: vkalintiris, dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D11139 llvm-svn: 247669
* [mips] Add missing disassembler tests for MIPS64-MIPS64R5.Daniel Sanders2015-09-1112-0/+990
| | | | llvm-svn: 247422
* [mips] Add missing MIPS32 - MIPS32R5 disassembler tests.Daniel Sanders2015-09-1112-0/+869
| | | | llvm-svn: 247420
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