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* Reland "[mips][mt][6/7] Add support for mftr, mttr instructions."Simon Dardis2017-11-142-2/+40
| | | | | | | | | | | | | | | | | | | | This adjusts the tests to hopfully pacify the llvm-clang-x86_64-expensive-checks-win buildbot. Unlike many other instructions, these instructions have aliases which take coprocessor registers, gpr register, accumulator (and dsp accumulator) registers, floating point registers, floating point control registers and coprocessor 2 data and control operands. For the moment, these aliases are treated as pseudo instructions which are expanded into the underlying instruction. As a result, disassembling these instructions shows the underlying instruction and not the alias. Reviewers: slthakur, atanasyan Differential Revision: https://reviews.llvm.org/D35253 llvm-svn: 318207
* Revert "Reland "[mips][mt][6/7] Add support for mftr, mttr instructions.""Simon Dardis2017-08-142-40/+2
| | | | | | | This reverts r310834. It didn't pacify the buildbot, FileCheck is still crashing. llvm-svn: 310854
* Reland "[mips][mt][6/7] Add support for mftr, mttr instructions."Simon Dardis2017-08-142-2/+40
| | | | | | | | | | | | | | | | | | | | This adjusts the tests to hopfully pacify the llvm-clang-x86_64-expensive-checks-win buildbot. Unlike many other instructions, these instructions have aliases which take coprocessor registers, gpr register, accumulator (and dsp accumulator) registers, floating point registers, floating point control registers and coprocessor 2 data and control operands. For the moment, these aliases are treated as pseudo instructions which are expanded into the underlying instruction. As a result, disassembling these instructions shows the underlying instruction and not the alias. Reviewers: slthakur, atanasyan Differential Revision: https://reviews.llvm.org/D35253 llvm-svn: 310834
* Revert "Reland "[mips][mt][6/7] Add support for mftr, mttr instructions.""Simon Dardis2017-07-142-40/+2
| | | | | | | | | FileCheck is crashing on in the input file, so reverting again while I investigate. This reverts r308023. llvm-svn: 308030
* Reland "[mips][mt][6/7] Add support for mftr, mttr instructions.""Simon Dardis2017-07-142-2/+40
| | | | | | | | | | | | | | | | | | | | | | | | Unlike many other instructions, these instructions have aliases which take coprocessor registers, gpr register, accumulator (and dsp accumulator) registers, floating point registers, floating point control registers and coprocessor 2 data and control operands. For the moment, these aliases are treated as pseudo instructions which are expanded into the underlying instruction. As a result, disassembling these instructions shows the underlying instruction and not the alias. Reviewers: slthakur, atanasyan Differential Revision: https://reviews.llvm.org/D35253 The last version of this patch broke one of the expensive checks buildbots, this version changes the failing test/MC/Mips/mt/invalid.s and other invalid tests to write the errors to a file and run FileCheck on that, rather than relying on the 'not llvm-mc ... <%s 2>&1 | Filecheck %s' idiom. Hopefully this will sarisfy the buildbot. llvm-svn: 308023
* Revert "[mips][mt][6/7] Add support for mftr, mttr instructions."Simon Dardis2017-07-132-40/+2
| | | | | | | This reverts r307836, it broke one of the buildbots. Reverting while I investigate. llvm-svn: 307939
* [mips][mt][6/7] Add support for mftr, mttr instructions.Simon Dardis2017-07-122-2/+40
| | | | | | | | | | | | | | | | | Unlike many other instructions, these instructions have aliases which take coprocessor registers, gpr register, accumulator (and dsp accumulator) registers, floating point registers, floating point control registers and coprocessor 2 data and control operands. For the moment, these aliases are treated as pseudo instructions which are expanded into the underlying instruction. As a result, disassembling these instructions shows the underlying instruction and not the alias. Reviewers: slthakur, atanasyan Differential Revision: https://reviews.llvm.org/D35253 llvm-svn: 307836
* [mips][mt][5/7] Add support for fork and yield instructions.Simon Dardis2017-07-122-0/+6
| | | | | | | | Reviewers: slthakur, atanasyan Differential Revision: https://reviews.llvm.org/D35252 llvm-svn: 307808
* [mips][mt][4/7] Add IAS support for dvpe, evpe instructions.Simon Dardis2017-07-122-0/+8
| | | | | | | | Reviewers: slthakur, atanasyan Differential Revision: https://reviews.llvm.org/D35251 llvm-svn: 307793
* [mips][mt] Add missing files from last commitSimon Dardis2017-07-122-0/+12
llvm-svn: 307779
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