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* [mips] Correct the predicates for special nops, tlb ctrl instrs, software ↵Simon Dardis2018-04-122-0/+2
| | | | | | | | | | breakpoint and prefx. Reviewers: atanasyan, abeserminji Differential Revision: https://reviews.llvm.org/D44436 llvm-svn: 329905
* Recommit: "[mips] Add rsqrt, recip for MIPS"Simon Dardis2016-10-053-4/+8
| | | | | | | | | | | Add rsqrt.[ds], recip.[ds] for MIPS. Correct the microMIPS definitions for architecture support and register usage. Reviewers: vkalintiris, zoran.jovanoic Differential Review: https://reviews.llvm.org/D24499 llvm-svn: 283334
* Revert "[mips] Add rsqrt, recip for MIPS"Simon Dardis2016-10-053-8/+4
| | | | | | | This reverts commit r282485 which contain two patches instead of one. llvm-svn: 283327
* [mips] Add rsqrt, recip for MIPSSimon Dardis2016-09-273-4/+8
| | | | | | | | | | | Add rsqrt.[ds], recip.[ds] for MIPS. Correct the microMIPS definitions for architecture support and register usage. Reviewers: vkalintiris, zoran.jovanoic Differential Review: https://reviews.llvm.org/D24499 llvm-svn: 282485
* [mips] Range check uimm16 and fix several bugs this revealed.Daniel Sanders2016-02-011-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: The bugs were: * teq and similar take 4-bit unsigned immediates on microMIPS. * teqi and similar have side-effects like teq do. * shll_s.w and shra_r.w take 5-bit unsigned immediates. * The various DSP ext* instructions take a 5-bit immediate. * repl.qh takes an 8-bit unsigned immediate. * repl.ph takes a 10-bit unsigned immediate. * rddsp/wrdsp take a 10-bit unsigned immediate. * teqi and similar take signed 16-bit immediates (10-bit for microMIPS). * Out-of-range immediate macros for or/xor take a simm32/simm64 depending on architecture. I'll fix the simm64 case properly when I reach simm32. lui is a bit more lenient than GAS and accepts signed immediates in addition to unsigned. This is because MipsMCExpr can produce signed values when constant folding and it currently lacks a way of knowing it should fold to an unsigned value. Reviewers: vkalintiris Subscribers: dsanders, llvm-commits Differential Revision: http://reviews.llvm.org/D15446 llvm-svn: 259360
* [mips][disassembler] Merged disassembler tests into the corresponding ↵Daniel Sanders2015-10-061-0/+30
| | | | | | ISA/ASE subdirectories. llvm-svn: 249384
* [mips] Add missing disassembler tests for MIPS64-MIPS64R5.Daniel Sanders2015-09-113-0/+237
| | | | llvm-svn: 247422
* [mips] Remap move as or.Vasileios Kalintiris2015-08-112-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | Summary: This patch remaps the assembly idiom 'move' to 'or' instead of 'daddu' or 'addu'. The use of addu/daddu instead of or as move was highlighted as a performance issue during the analysis of a recent 64bit design. Originally move was encoded as 'or' by binutils but was changed for the r10k cpu family due to their pipeline which had 2 arithmetic units and a single logical unit, and so could issue multiple (d)addu based moves at the same time but only 1 logical move. This patch preserves the disassembly behaviour so that disassembling a old style (d)addu move still appears as move, but assembling move always gives an or Patch by Simon Dardis. Reviewers: vkalintiris Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D11796 llvm-svn: 244579
* [mips] Fold duplicate big-endian disassembler tests together.Daniel Sanders2015-06-271-0/+30
| | | | llvm-svn: 240887
* [mips] Sort big-endian disassembler tests by opcode.Daniel Sanders2015-06-271-201/+201
| | | | llvm-svn: 240885
* [mips] Add COP0 register class and use it in M[FT]C0/DM[FT]C0.Daniel Sanders2015-06-272-0/+8
| | | | | | | | | | | | | | | | | Summary: Previously it (incorrectly) used GPR's. Patch by Simon Dardis. A couple small corrections by myself. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D10567 llvm-svn: 240883
* [mips][msa] Test basic operations for the N32 ABI too.Daniel Sanders2015-05-051-0/+2
| | | | | | | | | | | | | | | | | Summary: This required adding instruction aliases for dneg. N64 will be enabled shortly but requires additional bugfixes. Reviewers: vkalintiris Reviewed By: vkalintiris Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D9341 llvm-svn: 236489
* [mips] Add backend support for Mips32r[35] and Mips64r[35].Daniel Sanders2015-02-181-1/+1
| | | | | | | | | | | | | | | | | Summary: These ISA's didn't add any instructions so they are almost identical to Mips32r2 and Mips64r2. Even the ELF e_flags are the same, However the ISA revision in .MIPS.abiflags is 3 or 5 respectively instead of 2. Reviewers: vmedic Reviewed By: vmedic Subscribers: tomatabacu, llvm-commits, atanasyan Differential Revision: http://reviews.llvm.org/D7381 llvm-svn: 229695
* [mips] Merge disassemblers into a single implementation.Daniel Sanders2015-02-112-0/+6
| | | | | | | | | | | | | | | | | | | | Summary: Currently we have Mips32 and Mips64 disassemblers and this causes the target triple to affect the disassembly despite all the relevant information being in the ELF header. These implementations do not need to be separate. This patch merges them together such that the appropriate tables are checked for the subtarget (e.g. Mips64 is checked when GP64 is enabled). Reviewers: vmedic Reviewed By: vmedic Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D7498 llvm-svn: 228825
* [mips] 'CHECK :' is not a valid check directive. Fixed.Daniel Sanders2015-01-181-74/+74
| | | | llvm-svn: 226409
* [mips] Make whitespace in disassembler tests more consistent. NFC.Daniel Sanders2015-01-183-540/+540
| | | | | | | | | | The tests for the ISA's should now be approximately diffable. That is, the output of 'diff valid-mips1.txt valid-mips2.txt' should be emit the lines for instructions that were added/removed to/from MIPS-I by MIPS-II. This doesn't work perfectly at the moment due to ordering differences but it should be close. llvm-svn: 226408
* [mips] Make whitespace of disassembler tests more consistent by removing ↵Daniel Sanders2015-01-182-464/+0
| | | | | | blank lines. NFC. llvm-svn: 226407
* Add disassembler tests for mips64r2 platform. There are no functional changes.Vladimir Medic2015-01-153-0/+1008
llvm-svn: 226164
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