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* [mips] Add missing instructionsAleksandar Beserminji2018-08-292-0/+14
| | | | | | | | Add pll.ps, plu.ps, cvt.s.pu, cvt.s.pl, cvt.ps instructions for FP64. Differential Revision: https://reviews.llvm.org/D50437 llvm-svn: 340920
* [mips] Correct the predicates for special nops, tlb ctrl instrs, software ↵Simon Dardis2018-04-122-0/+2
| | | | | | | | | | breakpoint and prefx. Reviewers: atanasyan, abeserminji Differential Revision: https://reviews.llvm.org/D44436 llvm-svn: 329905
* [mips] Define certain instructions in microMIPS32r3Stefan Maksimovic2018-02-082-0/+24
| | | | | | | | | | | | | | | | | | | | Instructions affected: mthc1, mfhc1, add.d, sub.d, mul.d, div.d, mov.d, neg.d, cvt.w.d, cvt.d.s, cvt.d.w, cvt.s.d These instructions are now defined for microMIPS32r3 + microMIPS32r6 in MicroMipsInstrFPU.td since they shared their encoding with those already defined in microMIPS32r6InstrInfo.td and have been therefore removed from the latter file. Some instructions present in MicroMipsInstrFPU.td which did not have both AFGR64 and FGR64 variants defined have been altered to do so. Differential revision: https://reviews.llvm.org/D42738 llvm-svn: 324584
* [mips] Properly select abs and sqrt instructionsStefan Maksimovic2018-01-232-0/+14
| | | | | | | | | | | | | - Alter abs for micromips to have both AFGR64 and FGR64 variants, same as sqrt - Remove sqrt and abs from MicroMips32r6InstrInfo.td, use micromips FGR64 variants - Restrict non-micromips abs/sqrt with NotInMicroMips predicate Differential revision: https://reviews.llvm.org/D41439 llvm-svn: 323184
* [mips] Place certain 64 bit FPU instructions in their own decoder namespaceSimon Dardis2017-10-052-0/+2
| | | | | | | | | | | Previously, instructions that were defined to use the FGR64 register class were associated with the Mips64 table which was incorrect. Reviewers: nitesh.jain, atanasyan Differential Revision: https://reviews.llvm.org/D38454 llvm-svn: 314976
* Recommit: "[mips] Add rsqrt, recip for MIPS"Simon Dardis2016-10-053-4/+8
| | | | | | | | | | | Add rsqrt.[ds], recip.[ds] for MIPS. Correct the microMIPS definitions for architecture support and register usage. Reviewers: vkalintiris, zoran.jovanoic Differential Review: https://reviews.llvm.org/D24499 llvm-svn: 283334
* Revert "[mips] Add rsqrt, recip for MIPS"Simon Dardis2016-10-053-8/+4
| | | | | | | This reverts commit r282485 which contain two patches instead of one. llvm-svn: 283327
* [mips] Add rsqrt, recip for MIPSSimon Dardis2016-09-273-4/+8
| | | | | | | | | | | Add rsqrt.[ds], recip.[ds] for MIPS. Correct the microMIPS definitions for architecture support and register usage. Reviewers: vkalintiris, zoran.jovanoic Differential Review: https://reviews.llvm.org/D24499 llvm-svn: 282485
* [mips] Range check uimm16 and fix several bugs this revealed.Daniel Sanders2016-02-011-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: The bugs were: * teq and similar take 4-bit unsigned immediates on microMIPS. * teqi and similar have side-effects like teq do. * shll_s.w and shra_r.w take 5-bit unsigned immediates. * The various DSP ext* instructions take a 5-bit immediate. * repl.qh takes an 8-bit unsigned immediate. * repl.ph takes a 10-bit unsigned immediate. * rddsp/wrdsp take a 10-bit unsigned immediate. * teqi and similar take signed 16-bit immediates (10-bit for microMIPS). * Out-of-range immediate macros for or/xor take a simm32/simm64 depending on architecture. I'll fix the simm64 case properly when I reach simm32. lui is a bit more lenient than GAS and accepts signed immediates in addition to unsigned. This is because MipsMCExpr can produce signed values when constant folding and it currently lacks a way of knowing it should fold to an unsigned value. Reviewers: vkalintiris Subscribers: dsanders, llvm-commits Differential Revision: http://reviews.llvm.org/D15446 llvm-svn: 259360
* [mips] Add missing MIPS32 - MIPS32R5 disassembler tests.Daniel Sanders2015-09-113-0/+223
| | | | llvm-svn: 247420
* [mips] Sort big-endian disassembler tests by opcode.Daniel Sanders2015-06-271-142/+142
| | | | llvm-svn: 240885
* [mips] Make little-endian disassembler test filenames consistent.Daniel Sanders2015-06-271-0/+0
| | | | | | Most are named *-el.txt. Renamed the three that were *-le.txt llvm-svn: 240884
* [mips] Add COP0 register class and use it in M[FT]C0/DM[FT]C0.Daniel Sanders2015-06-272-0/+4
| | | | | | | | | | | | | | | | | Summary: Previously it (incorrectly) used GPR's. Patch by Simon Dardis. A couple small corrections by myself. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D10567 llvm-svn: 240883
* [mips] Add backend support for Mips32r[35] and Mips64r[35].Daniel Sanders2015-02-183-0/+421
Summary: These ISA's didn't add any instructions so they are almost identical to Mips32r2 and Mips64r2. Even the ELF e_flags are the same, However the ISA revision in .MIPS.abiflags is 3 or 5 respectively instead of 2. Reviewers: vmedic Reviewed By: vmedic Subscribers: tomatabacu, llvm-commits, atanasyan Differential Revision: http://reviews.llvm.org/D7381 llvm-svn: 229695
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