summaryrefslogtreecommitdiffstats
path: root/llvm/test/MC/Disassembler/Mips/mips32r3
Commit message (Collapse)AuthorAgeFilesLines
* [mips] Range check uimm16 and fix several bugs this revealed.Daniel Sanders2016-02-011-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: The bugs were: * teq and similar take 4-bit unsigned immediates on microMIPS. * teqi and similar have side-effects like teq do. * shll_s.w and shra_r.w take 5-bit unsigned immediates. * The various DSP ext* instructions take a 5-bit immediate. * repl.qh takes an 8-bit unsigned immediate. * repl.ph takes a 10-bit unsigned immediate. * rddsp/wrdsp take a 10-bit unsigned immediate. * teqi and similar take signed 16-bit immediates (10-bit for microMIPS). * Out-of-range immediate macros for or/xor take a simm32/simm64 depending on architecture. I'll fix the simm64 case properly when I reach simm32. lui is a bit more lenient than GAS and accepts signed immediates in addition to unsigned. This is because MipsMCExpr can produce signed values when constant folding and it currently lacks a way of knowing it should fold to an unsigned value. Reviewers: vkalintiris Subscribers: dsanders, llvm-commits Differential Revision: http://reviews.llvm.org/D15446 llvm-svn: 259360
* [mips] Add missing MIPS32 - MIPS32R5 disassembler tests.Daniel Sanders2015-09-113-0/+223
| | | | llvm-svn: 247420
* [mips] Sort big-endian disassembler tests by opcode.Daniel Sanders2015-06-271-142/+142
| | | | llvm-svn: 240885
* [mips] Make little-endian disassembler test filenames consistent.Daniel Sanders2015-06-271-0/+0
| | | | | | Most are named *-el.txt. Renamed the three that were *-le.txt llvm-svn: 240884
* [mips] Add COP0 register class and use it in M[FT]C0/DM[FT]C0.Daniel Sanders2015-06-272-0/+4
| | | | | | | | | | | | | | | | | Summary: Previously it (incorrectly) used GPR's. Patch by Simon Dardis. A couple small corrections by myself. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D10567 llvm-svn: 240883
* [mips] Add backend support for Mips32r[35] and Mips64r[35].Daniel Sanders2015-02-183-0/+421
Summary: These ISA's didn't add any instructions so they are almost identical to Mips32r2 and Mips64r2. Even the ELF e_flags are the same, However the ISA revision in .MIPS.abiflags is 3 or 5 respectively instead of 2. Reviewers: vmedic Reviewed By: vmedic Subscribers: tomatabacu, llvm-commits, atanasyan Differential Revision: http://reviews.llvm.org/D7381 llvm-svn: 229695
OpenPOWER on IntegriCloud