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* [mips] Add (dis)assembler tests for beqzl and bnezl instructions. NFCSimon Atanasyan2019-07-272-0/+4
| | | | llvm-svn: 367168
* [mips] Range check uimm16 and fix several bugs this revealed.Daniel Sanders2016-02-012-10/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: The bugs were: * teq and similar take 4-bit unsigned immediates on microMIPS. * teqi and similar have side-effects like teq do. * shll_s.w and shra_r.w take 5-bit unsigned immediates. * The various DSP ext* instructions take a 5-bit immediate. * repl.qh takes an 8-bit unsigned immediate. * repl.ph takes a 10-bit unsigned immediate. * rddsp/wrdsp take a 10-bit unsigned immediate. * teqi and similar take signed 16-bit immediates (10-bit for microMIPS). * Out-of-range immediate macros for or/xor take a simm32/simm64 depending on architecture. I'll fix the simm64 case properly when I reach simm32. lui is a bit more lenient than GAS and accepts signed immediates in addition to unsigned. This is because MipsMCExpr can produce signed values when constant folding and it currently lacks a way of knowing it should fold to an unsigned value. Reviewers: vkalintiris Subscribers: dsanders, llvm-commits Differential Revision: http://reviews.llvm.org/D15446 llvm-svn: 259360
* [mips] Never select JAL for calls to an absolute immediate address.Daniel Sanders2016-01-111-0/+1
| | | | | | | | | | | | | | | Summary: It actually takes an offset into the current PC-region. This fixes the 'expr' command in lldb. Reviewers: vkalintiris, jaydeep, bhushan Subscribers: dsanders, llvm-commits Differential Revision: http://reviews.llvm.org/D16054 llvm-svn: 257339
* [mips] Add missing MIPS-II disassembler tests.Daniel Sanders2015-09-113-0/+44
| | | | | | | These tests were found by llvm-mc-fuzzer (see http://reviews.llvm.org/D12723) and were verified by checking the disassembler output is accepted by GAS. llvm-svn: 247414
* [mips] Remap move as or.Vasileios Kalintiris2015-08-112-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | Summary: This patch remaps the assembly idiom 'move' to 'or' instead of 'daddu' or 'addu'. The use of addu/daddu instead of or as move was highlighted as a performance issue during the analysis of a recent 64bit design. Originally move was encoded as 'or' by binutils but was changed for the r10k cpu family due to their pipeline which had 2 arithmetic units and a single logical unit, and so could issue multiple (d)addu based moves at the same time but only 1 logical move. This patch preserves the disassembly behaviour so that disassembling a old style (d)addu move still appears as move, but assembling move always gives an or Patch by Simon Dardis. Reviewers: vkalintiris Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D11796 llvm-svn: 244579
* [mips] Fold duplicate big-endian disassembler tests together.Daniel Sanders2015-06-271-0/+4
| | | | llvm-svn: 240887
* [mips] Sort big-endian disassembler tests by opcode.Daniel Sanders2015-06-271-133/+131
| | | | llvm-svn: 240885
* [mips] Make whitespace in disassembler tests more consistent. NFC.Daniel Sanders2015-01-182-314/+314
| | | | | | | | | | The tests for the ISA's should now be approximately diffable. That is, the output of 'diff valid-mips1.txt valid-mips2.txt' should be emit the lines for instructions that were added/removed to/from MIPS-I by MIPS-II. This doesn't work perfectly at the moment due to ordering differences but it should be close. llvm-svn: 226408
* Add disassembler tests for mips2 platform. There are no functional changes.Vladimir Medic2014-12-152-0/+318
llvm-svn: 224252
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