| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | [Hexagon] Replace instruction definitions with auto-generated ones | Krzysztof Parzyszek | 2017-02-10 | 1 | -16/+16 |
| * | [Hexagon] Organizing tests and adding a few missing jump instruction encodings. | Colin LeMahieu | 2015-01-29 | 1 | -7/+19 |
| * | [Hexagon] Adding encoding for popcount, fastcorner, dword asr with rounding. | Colin LeMahieu | 2015-01-07 | 1 | -0/+4 |
| * | [Hexagon] Adding double-logic on predicate instructions. | Colin LeMahieu | 2014-12-30 | 1 | -2/+22 |
| * | [Hexagon] Adding transfers to and from control registers. | Colin LeMahieu | 2014-12-19 | 1 | -1/+5 |
| * | [Hexagon] Adding loop0/1 sp0/1/2loop0 instructions. | Colin LeMahieu | 2014-12-19 | 1 | -0/+20 |
| * | Reverting 224550, was not ready for commit. | Colin LeMahieu | 2014-12-18 | 1 | -20/+0 |
| * | [Hexagon] Adding loop0/1 sp0/1/2loop0 instructions. | Colin LeMahieu | 2014-12-18 | 1 | -0/+20 |
| * | [Hexagon] Adding any8, all8, and/or/xor/andn/orn/not predicate register forms... | Colin LeMahieu | 2014-12-08 | 1 | -0/+18 |
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index : bcm5719-llvm | |
| Project Ortega BCM5719 LLVM | Raptor Computing Systems |
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