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* VSTn instructions have a number of encoding constraints which are not ↵Mihai Popa2013-05-202-4/+45
| | | | | | implemented. I have added these using wrapper methods around the original custom decoder (incidentally - this is a huge poorly written method that should be cleaned up. I have left it as is since the changes would be much to hard to review). llvm-svn: 182281
* Q registers are encoded in fields of the same length as D registers. As Q ↵Mihai Popa2013-05-201-2/+2
| | | | | | registers are half as many, the ARM reference manual mandates the least significant bit to be zeroed out. Failure to do so should result in an undefined instruction. With this change test/MC/Disassembler/ARM/invalid-VQADD-arm.txt is passing (removed XFAIL). llvm-svn: 182279
* The purpose of the patch is to fix the syntax of ARM mrc and mrc2 ↵Mihai Popa2013-05-131-0/+4
| | | | | | instructions when they are used to write to the APSR. In this case, the destination operand should be APSR_nzcv, and the encoding of the target should be 0b1111 (same as for PC). In pre-UAL syntax, this form used the PC register as a textual target. This is still allowed for backward compatibility. llvm-svn: 181705
* s tightens up the encoding description for ARM post-indexed ldr ↵Mihai Popa2013-04-301-1/+0
| | | | | | instructions. All instructions in this class have bit 4 cleared. It turns out that there is a test case for this, but it was marked XFAIL. llvm-svn: 180778
* ARM: Fix encoding of hint instruction for Thumb.Quentin Colombet2013-04-262-0/+21
| | | | | | | | | | | | | | | "hint" space for Thumb actually overlaps the encoding space of the CPS instruction. In actuality, hints can be defined as CPS instructions where imod and M bits are all nil. Handle decoding of permitted nop-compatible hints (i.e. nop, yield, wfi, wfe, sev) in DecodeT2CPSInstruction. This commit adds a proper diagnostic message for Imm0_4 and updates all tests. Patch by Mihail Popa <Mihail.Popa@arm.com>. llvm-svn: 180617
* ARM: Permit "sp" in ARM variant of STREXD instructionsTim Northover2013-04-191-1/+2
| | | | | | Patch from Mihail Popa llvm-svn: 179854
* ARM: permit "sp" in ARM variants of MOVW/MOVT instructionsTim Northover2013-04-191-0/+6
| | | | llvm-svn: 179847
* ARM: Correct printing of pre-indexed operands.Quentin Colombet2013-04-121-0/+42
| | | | | | | | | | | | | According to the ARM reference manual, constant offsets are mandatory for pre-indexed addressing modes. The MC disassembler was not obeying this when the offset is 0. It was producing instructions like: str r0, [r1]!. Correct syntax is: str r0, [r1, #0]!. This change modifies the dumping of operands so that the offset is always printed, regardless of its value, when pre-indexed addressing mode is used. Patch by Mihail Popa <Mihail.Popa@arm.com> llvm-svn: 179398
* ARM: Make "SMC" instructions conditional on new TrustZone architecture feature.Tim Northover2013-04-103-9/+33
| | | | | | | | | | | | These instructions aren't universally available, but depend on a specific extension to the normal ARM architecture (rather than, say, v6/v7/...) so a new feature is appropriate. This also enables the feature by default on A-class cores which usually have these extensions, to avoid breaking existing code and act as a sensible default. llvm-svn: 179171
* Fix issue with disassembler decoding CBZ/CBNZ immediates as negatives when ↵Gordon Keiser2013-03-281-0/+3
| | | | | | | | the upper bit is set. They should always be zero-extended, not sign extended. Added test case. llvm-svn: 178275
* Patch by Gordon Keiser!Joe Abbey2013-03-261-0/+2
| | | | | | | | | | If PC or SP is the destination, the disassembler erroneously failed with the invalid encoding, despite the manual saying that both are fine. This patch addresses failure to decode encoding T4 of LDR (A8.8.62) which is a postindexed load, where the offset 0xc is applied to SP after the load occurs. llvm-svn: 178017
* Make ARMAsmPrinter generate the correct alignment specifier syntax in ↵Kristof Beyls2013-02-225-147/+147
| | | | | | | | | instructions. The Printer will now print instructions with the correct alignment specifier syntax, like vld1.8 {d16}, [r0:64] llvm-svn: 175884
* Make ARMAsmParser accept the correct alignment specifier syntax in instructions.Kristof Beyls2013-02-141-1/+1
| | | | | | | | | The parser will now accept instructions with alignment specifiers written like vld1.8 {d16}, [r0:64] , while also still accepting the incorrect syntax vld1.8 {d16}, [r0, :64] llvm-svn: 175164
* Added a option to the disassembler to print immediates as hex.Kevin Enderby2012-12-051-0/+5
| | | | | | | | | | | | | | | | | | | | This is for the lldb team so most of but not all of the values are to be printed as hex with this option. Some small values like the scale in an X86 address were requested to printed in decimal without the leading 0x. There may be some tweaks need to places that may still be in decimal that they want in hex. Specially for arm. I made my best guess. Any tweaks from here should be simple. I also did the best I know now with help from the C++ gurus creating the cleanest formatImm() utility function and containing the changes. But if someone has a better idea to make something cleaner I'm all ears and game for changing the implementation. rdar://8109283 llvm-svn: 169393
* Fixed the arm disassembly of invalid BFI instructions to not build a bad MCInstKevin Enderby2012-11-291-0/+11
| | | | | | which would then cause an assert when printed. rdar://11437956 llvm-svn: 168960
* ARM: Better disassembly for pc-relative LDR.Jim Grosbach2012-10-304-5/+7
| | | | | | | | | When the operand is a plain immediate rather than a label, print it as [pc, #imm] like we do for the Thumb2 wide encoding variant. rdar://12154503 llvm-svn: 166991
* Fix ARM's b.w instruction for thumb 2 and the encoding T4. The branch targetKevin Enderby2012-10-291-0/+3
| | | | | | | is 24 bits not 20 and the decoding needed to correctly handle converting the J1 and J2 bits to their I1 and I2 values to reconstruct the displacement. llvm-svn: 166982
* Add support for annotated disassembly output for X86 and arm.Kevin Enderby2012-10-221-0/+7
| | | | | | | | | | | Per the October 12, 2012 Proposal for annotated disassembly output sent out by Jim Grosbach this set of changes implements this for X86 and arm. The llvm-mc tool now has a -mdis option to produced the marked up disassembly and a couple of small example test cases have been added. rdar://11764962 llvm-svn: 166445
* Diagnose invalid alignments on duplicating VLDn instructions.Tim Northover2012-09-062-2/+6
| | | | | | Patch by Chris Lidbury. llvm-svn: 163323
* Check for invalid alignment values when decoding VLDn/VSTn (single ln) ↵Tim Northover2012-09-065-0/+93
| | | | | | | | instructions. Patch by Chris Lidbury. llvm-svn: 163321
* Use correct part of complex operand to encode VST1 alignment.Tim Northover2012-09-061-0/+77
| | | | | | Patch by Chris Lidbury. llvm-svn: 163318
* ARM: Move Thumb2 tests to Thumb2 test file and fix CHECK lines.Jim Grosbach2012-08-132-8/+10
| | | | | | These tests weren't actually being run before (missing ':' after CHECK). llvm-svn: 161800
* Fix #13035, a bug around Thumb instruction LDRD/STRD with negative #0 offset ↵Jiangning Liu2012-08-021-1/+11
| | | | | | index issue. llvm-svn: 161162
* Fix #13138, a bug around ARM instruction DSB encoding and decoding issue.Jiangning Liu2012-08-022-33/+93
| | | | llvm-svn: 161161
* Fix #13241, a bug around shift immediate operand for ARM instruction ADR.Jiangning Liu2012-08-022-0/+8
| | | | llvm-svn: 161159
* Fix instruction description of VMOV (between two ARM core registers and two ↵Richard Barton2012-07-101-1/+20
| | | | | | single-precision resiters) (and do it properly this time! llvm-svn: 159989
* Fix the remaining TCL-style quotes found in the testsuite. This isChandler Carruth2012-07-027-7/+7
| | | | | | | | | | | | | | | | | another mechanical change accomplished though the power of terrible Perl scripts. I have manually switched some "s to 's to make escaping simpler. While I started this to fix tests that aren't run in all configurations, the massive number of tests is due to a really frustrating fragility of our testing infrastructure: things like 'grep -v', 'not grep', and 'expected failures' can mask broken tests all too easily. Essentially, I'm deeply disturbed that I can change the testsuite so radically without causing any change in results for most platforms. =/ llvm-svn: 159547
* Convert the uses of '|&' to use '2>&1 |' instead, which works on oldChandler Carruth2012-07-0265-67/+67
| | | | | | | | | | versions of Bash. In addition, I can back out the change to the lit built-in shell test runner to support this. This should fix the majority of fallout on Darwin, but I suspect there will be a few straggling issues. llvm-svn: 159544
* Convert all tests using TCL-style quoting to use shell-style quoting.Chandler Carruth2012-07-0237-37/+37
| | | | | | | | | | | | | | | | | | | | | | | | This was done through the aid of a terrible Perl creation. I will not paste any of the horrors here. Suffice to say, it require multiple staged rounds of replacements, state carried between, and a few nested-construct-parsing hacks that I'm not proud of. It happens, by luck, to be able to deal with all the TCL-quoting patterns in evidence in the LLVM test suite. If anyone is maintaining large out-of-tree test trees, feel free to poke me and I'll send you the steps I used to convert things, as well as answer any painful questions etc. IRC works best for this type of thing I find. Once converted, switch the LLVM lit config to use ShTests the same as Clang. In addition to being able to delete large amounts of Python code from 'lit', this will also simplify the entire test suite and some of lit's architecture. Finally, the test suite runs 33% faster on Linux now. ;] For my 16-hardware-thread (2x 4-core xeon e5520): 36s -> 24s llvm-svn: 159525
* Correct decoder for T1 conditional B encodingRichard Barton2012-06-061-1/+10
| | | | llvm-svn: 158055
* Added the missing bit definition for the 4th bit of the STR (post reg) ↵Silviu Baranga2012-05-112-0/+67
| | | | | | instruction. It is now set to 0. The patch also sets the unpredictable mask for SEL and SXTB-type instructions. llvm-svn: 156609
* Fix issues with the ARM bl and blx thumb instructions and the J1 and J2 bitsKevin Enderby2012-05-031-0/+8
| | | | | | | | | for the assembler and disassembler. Which were not being set/read correctly for offsets greater than 22 bits in some cases. Changes to lib/Target/ARM/ARMAsmBackend.cpp from Gideon Myles! llvm-svn: 156118
* Fixed disassembler for vstm/vldm ARM VFP instructions.Silviu Baranga2012-05-031-0/+27
| | | | llvm-svn: 156077
* Disallow YIELD and other allocated nop hints in pre-ARMv6 architectures.Richard Barton2012-05-021-12/+0
| | | | llvm-svn: 155983
* Specify cpu to unbreak tests.Evan Cheng2012-04-2611-11/+11
| | | | llvm-svn: 155604
* Add missing test cases for ARM VLD3 (single 3-element structure to all lanes)Kevin Enderby2012-04-242-0/+38
| | | | | | instructions. llvm-svn: 155453
* Add missing test cases for ARM VLD4 (single 4-element structure to all lanes)Kevin Enderby2012-04-242-0/+49
| | | | | | instructions. llvm-svn: 155444
* Added support for disassembling unpredictable swp/swpb ARM instructions.Silviu Baranga2012-04-181-0/+26
| | | | llvm-svn: 155004
* Fix the bahavior of the disassembler when decoding unpredictable mrs ↵Silviu Baranga2012-04-181-0/+18
| | | | | | instructions on ARM. Now the diasassembler emmits warnings instead of errors. llvm-svn: 155002
* Added support for unpredictable mcrr/mcrr2/mrrc/mrrc2 ARM instruction in the ↵Silviu Baranga2012-04-182-0/+17
| | | | | | disassembler. Since the upredicability conditions are complex, C++ code was added to handle them. llvm-svn: 155001
* Fixed decoding for the ARM cdp2 instruction. The restriction on the ↵Silviu Baranga2012-04-181-0/+3
| | | | | | coprocessor number was removed for this instruction. llvm-svn: 155000
* Add suport for unpredicatble cases of the cmp, tst, teq and cmnz ARM ↵Silviu Baranga2012-04-181-0/+30
| | | | | | instructions in the disassembler. llvm-svn: 154999
* Fix ARM disassembly of VLD2 (single 2-element structure to all lanes)Kevin Enderby2012-04-172-0/+75
| | | | | | | instructions with writebacks. And add test a case for all opcodes handed by DecodeVLD2DupInstruction() in ARMDisassembler.cpp . llvm-svn: 154884
* Fixed a case of ARM disassembly getting an assert on a bad encodingKevin Enderby2012-04-111-0/+13
| | | | | | of a VST instruction. llvm-svn: 154544
* Fix ARM disassembly of VLD instructions with writebacks.  And add test a caseKevin Enderby2012-04-112-0/+364
| | | | | | for all opcodes handed by DecodeVLDInstruction() in ARMDisassembler.cpp . llvm-svn: 154459
* Fix a number of problems with ARM fused multiply add/subtract instructions.Evan Cheng2012-04-111-0/+37
| | | | | | | | | | 1. The new instruction itinerary entries are not properly described. 2. The asm parser can't handle vfms and vfnms. 3. There were no assembler, disassembler test cases. 4. HasNEON2 has the wrong assembler predicate. rdar://10139676 llvm-svn: 154456
* Added support for unpredictable ADC/SBC instructions on ARM, and also fixed ↵Silviu Baranga2012-04-051-0/+17
| | | | | | some corner cases involving the PC register as an operand for these instructions. llvm-svn: 154101
* Added support for handling unpredictable arithmetic instructions on ARM.Silviu Baranga2012-04-052-12/+7
| | | | llvm-svn: 154100
* Added fix in TableGen instruction decoder generation. The decoder now breaks ↵Silviu Baranga2012-04-021-0/+15
| | | | | | for every leaf node. llvm-svn: 153874
* Continue cleanup of LIT, getting rid of the remaining artifacts from dejagnuEli Bendersky2012-03-251-8/+1
| | | | | | | | | | | | | | * Removed test/lib/llvm.exp - it is no longer needed * Deleted the dg.exp reading code from test/lit.cfg. There are no dg.exp files left in the test suite so this code is no longer required. test/lit.cfg is now much shorter and clearer * Removed a lot of duplicate code in lit.local.cfg files that need access to the root configuration, by adding a "root" attribute to the TestingConfig object. This attribute is dynamically computed to provide the same information as was previously provided by the custom getRoot functions. * Documented the config.root attribute in docs/CommandGuide/lit.pod llvm-svn: 153408
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