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* [ARM][v8.5A] Add speculation barriers SSBB and PSSBBOliver Stannard2018-09-281-2/+2
| | | | | | | | | | | This adds two new barrier instructions which can be used to restrict speculative execution of load instructions. Patch by Pablo Barrio! Differential revision: https://reviews.llvm.org/D52484 llvm-svn: 343300
* Add support for ARM modified-immediate assembly syntax.Asiri Rathnayake2014-12-021-2/+108
| | | | | | | | | | | | | | | | | | | | Certain ARM instructions accept 32-bit immediate operands encoded as a 8-bit integer value (0-255) and a 4-bit rotation (0-30, even). Current ARM assembly syntax support in LLVM allows the decoded (32-bit) immediate to be specified as a single immediate operand for such instructions: mov r0, #4278190080 The ARMARM defines an extended assembly syntax allowing the encoding to be made more explicit, as in: mov r0, #255, #8 ; (same 32-bit value as above) The behaviour of the two instructions can be different w.r.t flags, which is documented under "Modified immediate constants" in ARMARM. This patch enables support for this extended syntax at the MC layer. llvm-svn: 223113
* [ARM] Introduce the 'sevl' instruction in ARMv8.Joey Gouly2013-10-011-0/+2
| | | | | | | This also removes the restriction on the immediate field of the 'hint' instruction. llvm-svn: 191744
* ARM: ISB cannot be passed the same options as DMBAmaury de la Vieuville2013-06-101-0/+2
| | | | | | ISB should only accepts full system sync, other options are reserved llvm-svn: 183656
* ARM: fix CPS decoding when ambiguous with QADDAmaury de la Vieuville2013-06-081-0/+4
| | | | | | | | | Handle the case when the disassembler table can't tell the difference between some encodings of QADD and CPS. Add some necessary safe guards in CPS decoding as well. llvm-svn: 183610
* This is a simple patch that changes RRX and RRXS to accept all registers as ↵Mihai Popa2013-06-051-0/+23
| | | | | | | | operands. According to the ARM reference manual, RRX(S) have defined encodings for lr, pc and sp. llvm-svn: 183307
* The purpose of the patch is to fix the syntax of ARM mrc and mrc2 ↵Mihai Popa2013-05-131-0/+4
| | | | | | instructions when they are used to write to the APSR. In this case, the destination operand should be APSR_nzcv, and the encoding of the target should be 0b1111 (same as for PC). In pre-UAL syntax, this form used the PC register as a textual target. This is still allowed for backward compatibility. llvm-svn: 181705
* ARM: Permit "sp" in ARM variant of STREXD instructionsTim Northover2013-04-191-1/+2
| | | | | | Patch from Mihail Popa llvm-svn: 179854
* ARM: permit "sp" in ARM variants of MOVW/MOVT instructionsTim Northover2013-04-191-0/+6
| | | | llvm-svn: 179847
* ARM: Make "SMC" instructions conditional on new TrustZone architecture feature.Tim Northover2013-04-101-9/+0
| | | | | | | | | | | | These instructions aren't universally available, but depend on a specific extension to the normal ARM architecture (rather than, say, v6/v7/...) so a new feature is appropriate. This also enables the feature by default on A-class cores which usually have these extensions, to avoid breaking existing code and act as a sensible default. llvm-svn: 179171
* Fix #13138, a bug around ARM instruction DSB encoding and decoding issue.Jiangning Liu2012-08-021-31/+61
| | | | llvm-svn: 161161
* Fix #13241, a bug around shift immediate operand for ARM instruction ADR.Jiangning Liu2012-08-021-0/+6
| | | | llvm-svn: 161159
* Specify cpu to unbreak tests.Evan Cheng2012-04-261-1/+1
| | | | llvm-svn: 155604
* Revert r142618, r142622, and r142624, which were based on an incorrect ↵Owen Anderson2011-10-201-5/+49
| | | | | | reading of the ARMv7 docs. llvm-svn: 142626
* Fix decoding tests for fixed MSR encodings.Owen Anderson2011-10-201-49/+5
| | | | llvm-svn: 142624
* Improve encoding support for BLX with immediat eoperands, and fix a BLX ↵Owen Anderson2011-08-261-0/+9
| | | | | | decoding bug this uncovered. llvm-svn: 138675
* Support an extension of ARM asm syntax to allow immediate operands to ADR ↵Owen Anderson2011-08-261-0/+8
| | | | | | instructions. This is helpful for disassembler testing, and indeed exposed a disassembler bug that is also fixed here. llvm-svn: 138635
* Fix incorrect encoding of UMAAL and friends. Patch by James Molloy.Owen Anderson2011-08-151-2/+2
| | | | llvm-svn: 137641
* Port over the basic ARM encodings test file to a decoding test file. ↵Owen Anderson2011-08-121-0/+2345
Greatly increases our test coverage of basic ARM-mode instructions. llvm-svn: 137495
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