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* [ARM] Fix disassembly for conditional VMRS and VMSR instructions in ARM modeAndre Vieira2017-10-181-0/+51
| | | | | | Differential Revision: https://reviews.llvm.org/D38347 llvm-svn: 316085
* [ARM] Fix assembly and disassembly for VMRS/VMSRAndre Vieira2017-09-221-0/+60
| | | | | | | Reviewed by: t.p.northover Differential Revision: https://reviews.llvm.org/D36306 llvm-svn: 313979
* Revert "[ARM] Fix assembly and disassembly for VMRS/VMSR"Tim Northover2017-08-081-60/+0
| | | | | | | | This reverts r310243. Only MVFR2 is actually restricted to v8 and it'll be a little while before we can get a proper fix together. Better that we allow incorrect code than reject correct in the meantime. llvm-svn: 310384
* [ARM] Fix assembly and disassembly for VMRS/VMSRAndre Vieira2017-08-071-0/+60
This patch addresses two issues with assembly and disassembly for VMRS/VMSR: 1.currently VMRS/VMSR instructions accessing fpsid, mvfr{0-2} and fpexc, are accepted for non ARMv8-A targets. 2. all VMRS/VMSR instructions accept writing/reading to PC and SP, when only ARMv7-A and ARMv8-A should be allowed to write/read to SP and none to PC. This patch addresses those issues and adds tests for these cases. Differential Revision: https://reviews.llvm.org/D36306 llvm-svn: 310243
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