| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | [lit] Delete empty lines at the end of lit.local.cfg NFC | Fangrui Song | 2019-06-17 | 1 | -1/+0 |
| | | | | | llvm-svn: 363538 | ||||
| * | [ARC] Add more load/store variants. | Pete Couperus | 2019-03-14 | 1 | -0/+47 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On ARC ISA, general format of load instruction is this: LD<zz><.x><.aa><.di> a, [b,c] And general format of store is this: ST<zz><.aa><.di> c, [b,s9] Where: <zz> is data size field and can be one of <empty> (bits 00) - Word (32-bit), default behavior B (bits 01) - Byte H (bits 10) - Half-word (16-bit) <.x> is data extend mode: <empty> (bit 0) - If size is not Word(32-bit), then data is zero extended X (bit 1) - If size is not Word(32-bit), then data is sign extended <.aa> is address write-back mode: <empty> (bits 00) - no write-back .AW (bits 01) - Preincrement, base register updated pre memory transaction .AB (bits 10) - Postincrement, base register updated post memory transaction <.di> is cache bypass mode: <empty> (bit 0) - Cached memory access, default mode .DI (bit 1) - Non-cached data memory access This patch adds these load/store instruction variants to the ARC backend. Patch By Denis Antrushin! <denis@synopsys.com> Differential Revision: https://reviews.llvm.org/D58980 llvm-svn: 356200 | ||||
| * | [ARC] Prevent InstPrinter from crashing on unknown condition codes. | Tatyana Krasnukha | 2018-09-06 | 1 | -0/+2 |
| | | | | | | | | | | | | | | Summary: Instruction printer shouldn't crash with assertions due to incorrect input data. llvm_unreachable is not intended for runtime error handling. Reviewers: petecoup Reviewed By: petecoup Differential Revision: https://reviews.llvm.org/D51728 llvm-svn: 341581 | ||||
| * | [ARC] Add LImm support for J/JL | Yan Luo | 2018-04-13 | 1 | -0/+6 |
| | | | | | llvm-svn: 330031 | ||||
| * | [ARC] Add <.f> suffix for F32_GEN4_{DOP|SOP}. | Pete Couperus | 2018-04-06 | 1 | -0/+24 |
| | | | | | | | | | | Add disassembler support for instructions which writeback STATUS32. https://reviews.llvm.org/D45148 Patch by Yan Luo! (Yan.Luo2@synopsys.com) llvm-svn: 329404 | ||||
| * | [ARC] Add instruction subset for the ARC backend. | Tatyana Krasnukha | 2017-12-02 | 3 | -0/+394 |
| | | | | | | | | | | | | | Reviewers: petecoup, kparzysz Reviewed By: petecoup Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D37983 llvm-svn: 319609 | ||||
| * | [ARC] Add ARC backend. | Pete Couperus | 2017-08-24 | 5 | -0/+196 |
| Add the ARC backend as an experimental target to lib/Target. Reviewed at: https://reviews.llvm.org/D36331 llvm-svn: 311667 | |||||
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index : bcm5719-llvm | |
| Project Ortega BCM5719 LLVM | Raptor Computing Systems |
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