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* Fixed a bug about disassembling AArch64 post-index load/store single element ↵Hao Liu2013-11-251-7/+7
| | | | | | | | | | instructions. ie. echo "0x00 0x04 0x80 0x0d" | ../bin/llvm-mc -triple=aarch64 -mattr=+neon -disassemble echo "0x00 0x00 0x80 0x0d" | ../bin/llvm-mc -triple=aarch64 -mattr=+neon -disassemble will be disassembled into the same instruction st1 {v0b}[0], [x0], x0. llvm-svn: 195591
* Implement AArch64 neon instructions class SIMD lsone and SIMD lone-post.Hao Liu2013-11-191-0/+84
| | | | llvm-svn: 195078
* Implement AArch64 NEON instruction set AdvSIMD (table).Jiangning Liu2013-11-141-1/+40
| | | | llvm-svn: 194648
* [AArch64] Implemented AdvSIMD scalar x indexed element format and AdvSIMD scalarChad Rosier2013-11-121-0/+213
| | | | | | | | copy in MC layer. Added the MC layer tests. Fixed triple setting in test cases. Patch by Ana Pazos <apazos@codeaurora.org>. llvm-svn: 194501
* [AArch64] Add support for NEON scalar floating-point convert to fixed-point ↵Chad Rosier2013-11-111-0/+16
| | | | | | instructions. llvm-svn: 194394
* Implement AArch64 Neon instruction set Perm.Jiangning Liu2013-11-061-0/+107
| | | | llvm-svn: 194123
* Implement AArch64 Neon instruction set Bitwise Extract.Jiangning Liu2013-11-061-0/+9
| | | | llvm-svn: 194118
* Implement AArch64 post-index vector load/store multiple N-element structure ↵Hao Liu2013-11-051-1/+72
| | | | | | | | | | | | class SIMD(lselem-post). Including following 14 instructions: 4 ld1 insts: post-index load multiple 1-element structure to sequential 1/2/3/4 registers. ld2/ld3/ld4: post-index load multiple N-element structure to sequential N registers (N=2,3,4). 4 st1 insts: post-index store multiple 1-element structure from sequential 1/2/3/4 registers. st2/st3/st4: post-index store multiple N-element structure from sequential N registers (N = 2,3,4). llvm-svn: 194043
* [AArch64] Add support for NEON scalar fixed-point convert to floating-point ↵Chad Rosier2013-10-311-0/+16
| | | | | | instructions. llvm-svn: 193816
* [AArch64] Add support for NEON scalar shift immediate instructions.Chad Rosier2013-10-311-0/+162
| | | | llvm-svn: 193790
* [AArch64] Make the use of FP instructions optional, but enabled by default.Amara Emerson2013-10-315-5/+5
| | | | | | | This adds a new subtarget feature called FPARMv8 (implied by NEON), and predicates the support of the FP instructions and registers on this feature. llvm-svn: 193739
* [AArch64] Add support for NEON scalar floating-point compare instructions.Chad Rosier2013-10-301-0/+80
| | | | llvm-svn: 193691
* [AArch64] Add support for NEON scalar extract narrow instructions.Chad Rosier2013-10-181-0/+30
| | | | llvm-svn: 192970
* [AArch64] Add support for NEON scalar three register different instructionChad Rosier2013-10-171-0/+24
| | | | | | | | class. The instruction class includes the signed saturating doubling multiply-add long, signed saturating doubling multiply-subtract long, and the signed saturating doubling multiply long instructions. llvm-svn: 192908
* [AArch64] Add support for NEON scalar negate instruction.Chad Rosier2013-10-161-0/+6
| | | | llvm-svn: 192843
* [AArch64] Add support for NEON scalar absolute value instruction.Chad Rosier2013-10-161-0/+6
| | | | llvm-svn: 192842
* Update comment.Chad Rosier2013-10-161-1/+1
| | | | llvm-svn: 192806
* [AArch64] Add support for NEON scalar signed saturating accumulated of unsignedChad Rosier2013-10-161-0/+24
| | | | | | value and unsigned saturating accumulate of signed value instructions. llvm-svn: 192800
* [AArch64] Add support for NEON scalar signed saturating absolute value andChad Rosier2013-10-151-0/+24
| | | | | | scalar signed saturating negate instructions. llvm-svn: 192733
* [AArch64] Add support for NEON scalar integer compare instructions.Chad Rosier2013-10-141-0/+67
| | | | llvm-svn: 192596
* [AArch64] Add support for NEON scalar floating-point reciprocal estimate,Chad Rosier2013-10-081-0/+24
| | | | | | reciprocal exponent, and reciprocal square root estimate instructions. llvm-svn: 192242
* [AArch64] Add support for NEON scalar signed/unsigned integer to floating-pointChad Rosier2013-10-081-0/+16
| | | | | | convert instructions. llvm-svn: 192231
* [AArch64] Add support for NEON scalar arithmetic instructions:Chad Rosier2013-10-071-0/+40
| | | | | | SQDMULH, SQRDMULH, FMULX, FRECPS, and FRSQRTS. llvm-svn: 192107
* AArch64: use RegisterOperand for NEON registers.Tim Northover2013-09-131-2/+5
| | | | | | | | | | | | | | | | Previously we modelled VPR128 and VPR64 as essentially identical register-classes containing V0-V31 (which had Q0-Q31 as "sub_alias" sub-registers). This model is starting to cause significant problems for code generation, particularly writing EXTRACT/INSERT_SUBREG patterns for converting between the two. The change here switches to classifying VPR64 & VPR128 as RegisterOperands, which are essentially aliases for RegisterClasses with different parsing and printing behaviour. This fits almost exactly with their real status (VPR128 == FPR128 printed strangely, VPR64 == FPR64 printed strangely). llvm-svn: 190665
* Implement aarch64 neon instruction set AdvSIMD (3V Diff), covering the ↵Jiangning Liu2013-09-091-0/+360
| | | | | | | | following 26 instructions, SADDL, UADDL, SADDW, UADDW, SSUBL, USUBL, SSUBW, USUBW, ADDHN, RADDHN, SABAL, UABAL, SUBHN, RSUBHN, SABDL, UABDL, SMLAL, UMLAL, SMLSL, UMLSL, SQDMLAL, SQDMLSL, SMULL, UMULL, SQDMULL, PMULL llvm-svn: 190288
* Inplement aarch64 neon instructions in AdvSIMD(shift). About 24 shift ↵Hao Liu2013-09-041-0/+395
| | | | | | | | | | instructions: sshr,ushr,ssra,usra,srshr,urshr,srsra,ursra,sri,shl,sli,sqshlu,sqshl,uqshl,shrn,sqrshrun,sqshrn,uqshr,sqrshrn,uqrshrn,sshll,ushll and 4 convert instructions: scvtf,ucvtf,fcvtzs,fcvtzu llvm-svn: 189925
* [tests] Cleanup initialization of test suffixes.Daniel Dunbar2013-08-161-2/+0
| | | | | | | | | | | | | | | | | - Instead of setting the suffixes in a bunch of places, just set one master list in the top-level config. We now only modify the suffix list in a few suites that have one particular unique suffix (.ml, .mc, .yaml, .td, .py). - Aside from removing the need for a bunch of lit.local.cfg files, this enables 4 tests that were inadvertently being skipped (one in Transforms/BranchFolding, a .s file each in DebugInfo/AArch64 and CodeGen/PowerPC, and one in CodeGen/SI which is now failing and has been XFAILED). - This commit also fixes a bunch of config files to use config.root instead of older copy-pasted code. llvm-svn: 188513
* Clang and AArch64 backend patches to support shll/shl and vmovl instructions ↵Hao Liu2013-08-151-0/+23
| | | | | | and ACLE functions llvm-svn: 188451
* AArch64: add initial NEON supportTim Northover2013-08-011-0/+673
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Patch by Ana Pazos. - Completed implementation of instruction formats: AdvSIMD three same AdvSIMD modified immediate AdvSIMD scalar pairwise - Completed implementation of instruction classes (some of the instructions in these classes belong to yet unfinished instruction formats): Vector Arithmetic Vector Immediate Vector Pairwise Arithmetic - Initial implementation of instruction formats: AdvSIMD scalar two-reg misc AdvSIMD scalar three same - Intial implementation of instruction class: Scalar Arithmetic - Initial clang changes to support arm v8 intrinsics. Note: no clang changes for scalar intrinsics function name mangling yet. - Comprehensive test cases for added instructions To verify auto codegen, encoding, decoding, diagnosis, intrinsics. llvm-svn: 187567
* AArch64: implement ETMv4 trace system registers.Tim Northover2013-04-031-0/+736
| | | | llvm-svn: 178637
* AArch64: implement GICv3 system registersTim Northover2013-03-281-0/+222
| | | | llvm-svn: 178236
* AArch64: remove post-encoder method from FCMP (immediate) instructions.Tim Northover2013-02-281-0/+8
| | | | | | | | The work done by the post-encoder (setting architecturally unused bits to 0 as required) can be done by the existing operand that covers the "#0.0". This removes at least one use of the discouraged PostEncoderMethod uses. llvm-svn: 176261
* Add AArch64 CRC32 instructionsTim Northover2013-02-061-0/+17
| | | | | | | | These instructions are a late addition to the architecture, and may yet end up behind an optional attribute, but for now they're available at all times. llvm-svn: 174496
* Add icache prefetch operations to AArch64Tim Northover2013-02-061-0/+38
| | | | | | | This adds hints to the various "prfm" instructions so that they can affect the instruction cache as well as the data cache. llvm-svn: 174495
* Add AArch64 as an experimental target.Tim Northover2013-01-317-0/+4331
This patch adds support for AArch64 (ARM's 64-bit architecture) to LLVM in the "experimental" category. Currently, it won't be built unless requested explicitly. This initial commit should have support for: + Assembly of all scalar (i.e. non-NEON, non-Crypto) instructions (except the late addition CRC instructions). + CodeGen features required for C++03 and C99. + Compilation for the "small" memory model: code+static data < 4GB. + Absolute and position-independent code. + GNU-style (i.e. "__thread") TLS. + Debugging information. The principal omission, currently, is performance tuning. This patch excludes the NEON support also reviewed due to an outbreak of batshit insanity in our legal department. That will be committed soon bringing the changes to precisely what has been approved. Further reviews would be gratefully received. llvm-svn: 174054
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