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* [ARM] NEON 32-bit scalar moves are also available in VFPv2Oliver Stannard2014-10-211-0/+32
| | | | | | | | | | | The 32-bit variants of the NEON scalar<->GPR move instructions are also available in VFPv2. The 8- and 16-bit variants do require NEON. Note that the checks in the test file are all -DAG because they are checking a mixture of stdout and stderr, and the ordering is not guaranteed. llvm-svn: 220288
* [Thumb2] LDRS?[BH] cannot load to the PCOliver Stannard2014-10-211-0/+51
| | | | | | | The Thumb2 LDRS?[BH] instructions are not valid when the destination register is the PC (these encodings are used for preload hints). llvm-svn: 220278
* [Thumb2] RFE, SRS and "SUBS pc, lr" are undefined on v7MOliver Stannard2014-10-201-0/+15
| | | | | | | These instructions are related to the v7[AR] exception model, and are not defined on v7M. llvm-svn: 220204
* Revert "Revert "DI: Fold constant arguments into a single MDString""Duncan P. N. Exon Smith2014-10-031-5/+5
| | | | | | | | | | | | | | | | | | | | | | This reverts commit r218918, effectively reapplying r218914 after fixing an Ocaml bindings test and an Asan crash. The root cause of the latter was a tightened-up check in `DILexicalBlock::Verify()`, so I'll file a PR to investigate who requires the loose check (and why). Original commit message follows. -- This patch addresses the first stage of PR17891 by folding constant arguments together into a single MDString. Integers are stringified and a `\0` character is used as a separator. Part of PR17891. Note: I've attached my testcases upgrade scripts to the PR. If I've just broken your out-of-tree testcases, they might help. llvm-svn: 219010
* Revert "DI: Fold constant arguments into a single MDString"Duncan P. N. Exon Smith2014-10-021-5/+5
| | | | | | This reverts commit r218914 while I investigate some bots. llvm-svn: 218918
* DI: Fold constant arguments into a single MDStringDuncan P. N. Exon Smith2014-10-021-5/+5
| | | | | | | | | | | | | This patch addresses the first stage of PR17891 by folding constant arguments together into a single MDString. Integers are stringified and a `\0` character is used as a separator. Part of PR17891. Note: I've attached my testcases upgrade scripts to the PR. If I've just broken your out-of-tree testcases, they might help. llvm-svn: 218914
* [Thumb2] ldrexd and strexd are not defined on v7MOliver Stannard2014-09-291-0/+14
| | | | | | | The Thumb2 ldrexd and strexd instructions are not defined for M-class architectures. llvm-svn: 218603
* Elide repeated register operand in Thumb1 instructionsRenato Golin2014-09-261-0/+52
| | | | | | | | | | | | | | | | | | | This patch makes the ARM backend transform 3 operand instructions such as 'adds/subs' to the 2 operand version of the same instruction if the first two register operands are the same. Example: 'adds r0, r0, #1' will is transformed to 'adds r0, #1'. Currently for some instructions such as 'adds' if you try to assemble 'adds r0, r0, #8' for thumb v6m the assembler would throw an error message because the immediate cannot be encoded using 3 bits. The backend should be smart enough to transform the instruction to 'adds r0, #8', which allows for larger immediate constants. Patch by Ranjeet Singh. llvm-svn: 218521
* Add aliases for VAND imm to VBIC ~immRenato Golin2014-09-252-18/+86
| | | | | | | | | | | | | On ARM NEON, VAND with immediate (16/32 bits) is an alias to VBIC ~imm with the same type size. Adding that logic to the parser, and generating VBIC instructions from VAND asm files. This patch also fixes the validation routines for NEON splat immediates which were wrong. Fixes PR20702. llvm-svn: 218450
* [Thumb2] BXJ should be undefined for v7M, v8AOliver Stannard2014-09-251-0/+10
| | | | | | | | The Thumb2 BXJ instruction (Branch and Exchange Jazelle) is not defined for v7M or v8A. It is defined for all other Thumb2-supporting architectures (v6T2, v7A and v7R). llvm-svn: 218445
* [Thumb] 32-bit encodings of 'cps' are not valid for v7MOliver Stannard2014-09-241-0/+17
| | | | | | | | v7M only allows the 16-bit encoding of the 'cps' (Change Processor State) instruction, and does not have the 32-bit encoding which is valid from v6T2 onwards. llvm-svn: 218382
* Downgrade DWARF2 section limit error to a warningOliver Stannard2014-09-222-2/+68
| | | | | | | | | We currently emit an error when trying to assemble a file with more than one section using DWARF2 debug info. This should be a warning instead, as the resulting file will still be usable, but with a degraded debug illusion. llvm-svn: 218241
* llvm-readobj: pretty-print special COFF section namesDavid Majnemer2014-09-201-3/+3
| | | | | | Print IMAGE_SYM_DEBUG and the like instead of (-2). llvm-svn: 218172
* ARM: prevent crash on ELF directives on COFFSaleem Abdulrasool2014-09-181-0/+68
| | | | | | | | | | Certain directives are unsupported on Windows (some of which could/should be supported). We would not diagnose the use but rather crash during the emission as we try to access the Target Streamer. Add an assertion to prevent creating a NULL reference (which is not permitted under C++) as well as a test to ensure that we can diagnose the disabled directives. llvm-svn: 218014
* ARM: use a more precise check for MachOSaleem Abdulrasool2014-09-181-0/+22
| | | | | | | | | | Rather than relying on support for a specific directive to determine if we are targeting MachO, explicitly check the output format. As an additional bonus, cleanup the caret diagnostic for the non-MachO case and avoid the spurious error caused by not discarding the statement. llvm-svn: 218012
* Object: Add support for bigobjDavid Majnemer2014-09-101-3/+3
| | | | | | | | | | | | | | | | | | | | | | This adds support for reading the "bigobj" variant of COFF produced by cl's /bigobj and mingw's -mbig-obj. The most significant difference that bigobj brings is more than 2**16 sections to COFF. bigobj brings a few interesting differences with it: - It doesn't have a Characteristics field in the file header. - It doesn't have a SizeOfOptionalHeader field in the file header (it's only used in executable files). - Auxiliary symbol records have the same width as a symbol table entry. Since symbol table entries are bigger, so are auxiliary symbol records. Write support will come soon. Differential Revision: http://reviews.llvm.org/D5259 llvm-svn: 217496
* Thumb2 M-class MSR instruction support changesRenato Golin2014-09-012-27/+72
| | | | | | | | | | | | This patch implements a few changes related to the Thumb2 M-class MSR instruction: * better handling of unpredictable encodings, * recognition of the _g and _nzcvqg variants by the asm parser only if the DSP extension is available, preferred output of MSR APSR moves with the _<bits> suffix for v7-M. Patch by Petr Pavlu. llvm-svn: 216874
* ARM: correct toggling behaviourSaleem Abdulrasool2014-08-171-0/+8
| | | | | | | | | | This was a thinko. The intent was to flip the explicit bits that need toggling rather than all bits. This would result in incorrect behaviour (which now is tested). Thanks to Nico Weber for pointing this out! llvm-svn: 215846
* arm asm: Let .fpu enable instructions, PR20447.Nico Weber2014-08-161-0/+16
| | | | | | | | | I'm not very happy with duplicating the fpu->feature mapping in ARMAsmParser.cpp and in clang's driver. See the bug for a patch that doesn't do that, and the review thread [1] for why this duplication exists. 1: http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20140811/231052.html llvm-svn: 215811
* ARM: implement MRS/MSR (banked reg) system instructions.Tim Northover2014-08-151-0/+220
| | | | | | | | | | These are system-only instructions for CPUs with virtualization extensions, allowing a hypervisor easy access to all of the various different AArch32 registers. rdar://problem/17861345 llvm-svn: 215700
* Add tests for cp10/cp11 on ARMv5/6Renato Golin2014-08-051-0/+10
| | | | | | Tests for ARMv7/8 are already on diagnostics.s llvm-svn: 214872
* Specify that the thumb setend and blx <immed> instructions are not valid on ↵Keith Walker2014-08-051-0/+26
| | | | | | an m-class target llvm-svn: 214871
* Define stc2/stc2l/ldc2/ldc2l as thumb2 instructionsKeith Walker2014-08-051-0/+11
| | | | llvm-svn: 214868
* [ARM] Make the assembler reject unpredictable pre/post-indexed ARM ↵Tilmann Scheller2014-08-011-0/+32
| | | | | | | | LDRB/LDRSB instructions. The ARM ARM prohibits LDRB/LDRSB instructions with writeback into the destination register. With this commit this constraint is now enforced and we stop assembling LDRH/LDRSH instructions with unpredictable behavior. llvm-svn: 214500
* [ARM] Make the assembler reject unpredictable pre/post-indexed ARM ↵Tilmann Scheller2014-08-011-0/+32
| | | | | | | | LDRH/LDRSH instructions. The ARM ARM prohibits LDRH/LDRSH instructions with writeback into the source register. With this commit this constraint is now enforced and we stop assembling LDRH/LDRSH instructions with unpredictable behavior. llvm-svn: 214499
* [ARM] Make the assembler reject unpredictable pre/post-indexed ARM LDR ↵Tilmann Scheller2014-08-011-0/+17
| | | | | | | | instructions. The ARM ARM prohibits LDR instructions with writeback into the destination register. With this commit this constraint is now enforced and we stop assembling LDR instructions with unpredictable behavior. llvm-svn: 214498
* ARM: correct handling of features in arch_extensionSaleem Abdulrasool2014-07-275-234/+142
| | | | | | | | | | | | | | | | | | | | | | The subtarget information is the ultimate source of truth for the feature set that is enabled at this point. We would previously not propagate the feature information to the subtarget. While this worked for the most part (features would be enabled/disabled as requested), if another operation that changed the feature bits was encountered (such as a mode switch via a .arm or .thumb directive), we would end up resetting the behaviour of the architectural extensions. Handling this properly requires a slightly more complicated handling. We need to check if the feature is now being toggled. If so, only then do we toggle the features. In return, we no longer have to calculate the feature bits ourselves. The test changes are mostly to the diagnosis, which is now more uniform (a nice side effect!). Add an additional test to ensure that we handle this case properly. Thanks to Nico Weber for alerting me to this issue! llvm-svn: 214057
* [ARM] Make the assembler reject unpredictable pre/post-indexed ARM STRH ↵Tilmann Scheller2014-07-241-0/+16
| | | | | | | | instructions. The ARM ARM prohibits STRH instructions with writeback into the source register. With this commit this constraint is now enforced and we stop assembling STRH instructions with unpredictable behavior. llvm-svn: 213850
* [ARM] Make the assembler reject unpredictable pre/post-indexed ARM STRB ↵Tilmann Scheller2014-07-231-0/+16
| | | | | | | | instructions. The ARM ARM prohibits STRB instructions with writeback into the source register. With this commit this constraint is now enforced and we stop assembling STRB instructions with unpredictable behavior. llvm-svn: 213750
* [ARM] Make the assembler reject unpredictable pre/post-indexed ARM STR ↵Tilmann Scheller2014-07-231-0/+17
| | | | | | | | instructions. The ARM ARM prohibits STR instructions with writeback into the source register. With this commit this constraint is now enforced and we stop assembling STR instructions with unpredictable behavior. llvm-svn: 213745
* MC: support different sized constants in constant poolsDavid Peixotto2014-07-182-16/+22
| | | | | | | | | | | | | | | On AArch64 the pseudo instruction ldr <reg>, =... supports both 32-bit and 64-bit constants. Add support for 64 bit constants for the pools to support the pseudo instruction fully. Changes the AArch64 ldr-pseudo tests to use 32-bit registers and adds tests with 64-bit registers. Patch by Janne Grunau! Differential Revision: http://reviews.llvm.org/D4279 llvm-svn: 213387
* ARM: when falling back to scattered relocs, keep the type.Tim Northover2014-07-041-0/+34
| | | | | | | | | | The linker relies on relocation type info (e.g. is it a branch?) to perform the correct actions, so we should keep that even when we end up using a scattered relocation for whatever reason. rdar://problem/17553104 llvm-svn: 212333
* ARM: take care not to set the ThumbFunc bit on TLS data symbolsScott Douglass2014-06-301-0/+26
| | | | | | | | This fixes LNT SingleSource/UnitTests/Threads with -mthumb. Differential Revision: http://reviews.llvm.org/D4324 llvm-svn: 212029
* Added parsing co-processor names starting with "cr"Renato Golin2014-06-261-0/+14
| | | | | | | | | | Additional compliant GAS names for coprocessor register name are enabled for all instruction with parameter MCK_CoprocReg: LDC,LDC2,STC,STC2,CDP,CDP2,MCR,MCR2,MCRR,MCRR2,MRC,MRC2,MRRC,MRRC2 Patch by Andrey Kuharev. llvm-svn: 211776
* ARM: mark UBFX as not allowing PC.Tim Northover2014-06-231-0/+18
| | | | | | | | | Strictly, it's unpredictable. But we don't quite model that yet and an error is better than ignoring the issue. This one somehow got left out before though. rdar://problem/15997748 llvm-svn: 211490
* MC: adjust text section flags for WoASaleem Abdulrasool2014-06-221-0/+58
| | | | | | | | | | | | | | | | | | | | | | | Correct the section flags for code built for Windows on ARM with `-ffunction-sections`. Windows on ARM uses solely Thumb-2 instructions, and indicates that the function is thumb by placing it in a text section that has IMAGE_SCN_MEM_16BIT flag set. When we encounter a .section directive, a new section is constructed. This may be a text segment. In order to identify that we need the additional flag, expose the target triple through the ObjectFileInfo as this information is lost otherwise. Since any modern ARM targeting environment on Windows would be Thumb-2 (Windows ARM NT or Windows Embedded Compact), introducing a new flag to indicate the section attribute seems to be a bit overkill. Simply depend on the target triple. Since there is one location that this information is currently needed, creating a target specific assembly parser and delegating the parsing of section switches also feels a bit heavy handed. If it turns out that this information ends up changing additional behaviour, then it may be worth considering that alternative. llvm-svn: 211481
* Since we're using DW_AT_string rather than DW_AT_strp for debug_infoEric Christopher2014-06-193-8/+8
| | | | | | | | for assembly files we can't depend on the offset within the section after a string since it could be different between producers etc. Relax these tests accordingly. llvm-svn: 211308
* Tests for r211273Oliver Stannard2014-06-194-0/+219
| | | | llvm-svn: 211279
* Reduce verbiage of lit.local.cfg filesAlp Toker2014-06-092-4/+2
| | | | | | We can just split targets_to_build in one place and make it immutable. llvm-svn: 210496
* MC: fix text section characteristics for WoASaleem Abdulrasool2014-06-081-0/+30
| | | | | | | | | | link.exe requires that the text section has the IMAGE_SCN_MEM_16BIT flag set. Otherwise, it will treat the function as ARM. If this occurs, then jumps to the function will fail, switching from thumb to ARM mode execution. With this change, it is possible to link using the MSVC linker as well. llvm-svn: 210415
* DebugInfo: Generalize some tests to handle variations in attribute ordering.David Blaikie2014-05-231-2/+0
| | | | | | | | | | | | | | | | In an effort to fix inlined debug info in situations where the out of line definition of a function preceeds any inlined usage, the order in which some attributes are added to subprogram DIEs may change. (in essence, definition-necessary attributes like DW_AT_low_pc/high_pc will be added immediately, but the names, types, and other features will be delayed to module end where they may either be added to the subprogram DIE or instead reference an abstract definition for those values) These tests can be generalized to be resilient to this change. 5 or so tests actually have to be incompatibly changed to cope with this reordering and will go along with the change that affects the order. llvm-svn: 209554
* MC: correct IMAGE_REL_ARM_MOV32T relocation emissionSaleem Abdulrasool2014-05-211-0/+37
| | | | | | | | | | | | This corrects the emission of IMAGE_REL_ARM_MOV32T relocations. Previously, we were avoiding the high portion of the relocation too early. If there was a section-relative relocation with an offset greater than 16-bits (65535), you would end up truncating the high order bits of the offset. Allow the current relocation representation to flow through out the MC layer to the object writer. Use the new ability to restrict recorded relocations to avoid emitting the relocation into the final object. llvm-svn: 209337
* ARMEB: Additional test files for ARM fixupsChristian Pirker2014-05-203-0/+219
| | | | llvm-svn: 209200
* ARM: implement support for the UDF mnemonicSaleem Abdulrasool2014-05-146-0/+98
| | | | | | | | | | | | | | The UDF instruction is a reserved undefined instruction space. The assembler mnemonic was introduced with ARM ARM rev C.a. The instruction is not predicated and the immediate constant is ignored by the CPU. Add support for the three encodings for this instruction. The changes to the invalid instruction test is due to the fact that the invalid instructions actually overlap with the undefined instruction. Introduction of the new instruction results in a partial decode as an undefined sequence. Drop the tests as they are invalid instruction patterns anyways. llvm-svn: 208751
* ARM: Additional test files for thumb fixups (checked with llvm-mv ↵Christian Pirker2014-05-134-44/+32
| | | | | | -show-encoding) llvm-svn: 208712
* ARM: Additional test files for thumb fixupsChristian Pirker2014-05-133-0/+36
| | | | llvm-svn: 208691
* test: fix silly typoSaleem Abdulrasool2014-05-081-1/+1
| | | | | | Oh silly Darwin and your case insensitive file system. llvm-svn: 208274
* ARM: support FK_SecRel_2 relocations on WoASaleem Abdulrasool2014-05-081-14/+24
| | | | | | | | This adds FK_SecRel_2 relocation support to ARM. This enables the building of object files for armv7-windows-msvc which enables CodeView line tables for debugging as opposed to armv7-windows-itanium which currently uses DWARF. llvm-svn: 208273
* ARM: For thumb fixups store halfwords high first and low secondChristian Pirker2014-05-061-0/+12
| | | | llvm-svn: 208076
* Fix spelling.Joerg Sonnenberger2014-05-051-0/+0
| | | | llvm-svn: 207982
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