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* MC: fix text section characteristics for WoASaleem Abdulrasool2014-06-081-0/+30
| | | | | | | | | | link.exe requires that the text section has the IMAGE_SCN_MEM_16BIT flag set. Otherwise, it will treat the function as ARM. If this occurs, then jumps to the function will fail, switching from thumb to ARM mode execution. With this change, it is possible to link using the MSVC linker as well. llvm-svn: 210415
* DebugInfo: Generalize some tests to handle variations in attribute ordering.David Blaikie2014-05-231-2/+0
| | | | | | | | | | | | | | | | In an effort to fix inlined debug info in situations where the out of line definition of a function preceeds any inlined usage, the order in which some attributes are added to subprogram DIEs may change. (in essence, definition-necessary attributes like DW_AT_low_pc/high_pc will be added immediately, but the names, types, and other features will be delayed to module end where they may either be added to the subprogram DIE or instead reference an abstract definition for those values) These tests can be generalized to be resilient to this change. 5 or so tests actually have to be incompatibly changed to cope with this reordering and will go along with the change that affects the order. llvm-svn: 209554
* MC: correct IMAGE_REL_ARM_MOV32T relocation emissionSaleem Abdulrasool2014-05-211-0/+37
| | | | | | | | | | | | This corrects the emission of IMAGE_REL_ARM_MOV32T relocations. Previously, we were avoiding the high portion of the relocation too early. If there was a section-relative relocation with an offset greater than 16-bits (65535), you would end up truncating the high order bits of the offset. Allow the current relocation representation to flow through out the MC layer to the object writer. Use the new ability to restrict recorded relocations to avoid emitting the relocation into the final object. llvm-svn: 209337
* ARMEB: Additional test files for ARM fixupsChristian Pirker2014-05-203-0/+219
| | | | llvm-svn: 209200
* ARM: implement support for the UDF mnemonicSaleem Abdulrasool2014-05-146-0/+98
| | | | | | | | | | | | | | The UDF instruction is a reserved undefined instruction space. The assembler mnemonic was introduced with ARM ARM rev C.a. The instruction is not predicated and the immediate constant is ignored by the CPU. Add support for the three encodings for this instruction. The changes to the invalid instruction test is due to the fact that the invalid instructions actually overlap with the undefined instruction. Introduction of the new instruction results in a partial decode as an undefined sequence. Drop the tests as they are invalid instruction patterns anyways. llvm-svn: 208751
* ARM: Additional test files for thumb fixups (checked with llvm-mv ↵Christian Pirker2014-05-134-44/+32
| | | | | | -show-encoding) llvm-svn: 208712
* ARM: Additional test files for thumb fixupsChristian Pirker2014-05-133-0/+36
| | | | llvm-svn: 208691
* test: fix silly typoSaleem Abdulrasool2014-05-081-1/+1
| | | | | | Oh silly Darwin and your case insensitive file system. llvm-svn: 208274
* ARM: support FK_SecRel_2 relocations on WoASaleem Abdulrasool2014-05-081-14/+24
| | | | | | | | This adds FK_SecRel_2 relocation support to ARM. This enables the building of object files for armv7-windows-msvc which enables CodeView line tables for debugging as opposed to armv7-windows-itanium which currently uses DWARF. llvm-svn: 208273
* ARM: For thumb fixups store halfwords high first and low secondChristian Pirker2014-05-061-0/+12
| | | | llvm-svn: 208076
* Fix spelling.Joerg Sonnenberger2014-05-051-0/+0
| | | | llvm-svn: 207982
* MC: support FK_SecRel_4 for Windows on ARMSaleem Abdulrasool2014-05-041-0/+41
| | | | | | | | | Add handling for FK_SecRel_4 (4-byte section relative relocations). These are used by the generation of DWARF debug information (the abbrevations use section relative relocations). This will also be used in generation of CodeView line tables. llvm-svn: 207941
* MC: place .file records into the correct sectionSaleem Abdulrasool2014-05-021-0/+30
| | | | | | | | | .file records are supposed to have a section identifier of 65534 (IMAGE_SCN_DEBUG) rather than 0. This is spelt out clearly within the PE/COFF specification. Fix this minor oversight with the implementation for support for .file records. llvm-svn: 207851
* Don't force symbols to be globals in .thumb_set.Rafael Espindola2014-05-011-15/+10
| | | | | | | | | | | | | | | | | | | | | | We currently force symbols to be globals in .thumb_set. The intent seems to be that given .thumb_set foo, bar we emit an undefined symbol to bar if it is never defined. The side effect is that we mark bar as global, even if it is defined, which gas does not. Producing an undefined reference to bar is a general difference from MC and gas. For example, given a = b gas will produce an undefined reference to b, MC will not. I would be surprised if any code depends on this, but it it does, we should fix the general difference, not special case .thumb_set. llvm-svn: 207757
* Correction to assert statemtent to allow 32-bit unsigned numbers with the ↵Richard Barton2014-05-011-0/+7
| | | | | | | | top bit set. This fixes an ARM assembler crash - regression test added. llvm-svn: 207747
* ARM: print COFF function header for Windows on ARMSaleem Abdulrasool2014-04-301-0/+45
| | | | | | | | | Emit the COFF header when printing out the function. This is important as the header contains two important pieces of information: the storage class for the symbol and the symbol type information. This bit of information is required for the linker to correctly identify the type of symbol that it is dealing with. llvm-svn: 207613
* Parse and create GOT_PREL relocations.Joerg Sonnenberger2014-04-291-0/+6
| | | | llvm-svn: 207526
* Centralize the handling of the thumb bit.Rafael Espindola2014-04-291-0/+15
| | | | | | | | | | | | | This patch centralizes the handling of the thumb bit around MCStreamer::isThumbFunc and makes isThumbFunc handle aliases. This fixes a corner case, but the main advantage is having just one way to check if a MCSymbol is thumb or not. This should still be refactored to be ARM only, but at least now it is just one predicate that has to be refactored instead of 3 (isThumbFunc, ELF_Other_ThumbFunc, and SF_ThumbFunc). llvm-svn: 207522
* Add emitThumbSet to the arm target streamer.Rafael Espindola2014-04-271-0/+5
| | | | | | | This fixes the asm printer implementation and lets the parser be unaware of what .thumb_set is. llvm-svn: 207381
* MC: duplicate .file test for WoA (SVN r207341)Saleem Abdulrasool2014-04-271-0/+17
| | | | | | | Since the COFF tests are dependent on X86, duplicate the test for ARM. Use the default check prefix. llvm-svn: 207365
* COFF: move ARM COFF test to ARM directorySaleem Abdulrasool2014-04-271-0/+101
| | | | | | | The COFF tests all assume X86. Just move the new COFF tests under ARM to appease the build bots. llvm-svn: 207346
* Fix for PR18921, "vmov" part.Stepan Dyatkovskiy2014-04-243-0/+103
| | | | | | | | | | | | | | | | | | | | | | | Added support for bytes replication feature, so it could be GAS compatible. E.g. instructions below: "vmov.i32 d0, 0xffffffff" "vmvn.i32 d0, 0xabababab" "vmov.i32 d0, 0xabababab" "vmov.i16 d0, 0xabab" are incorrect, but we could deal with such cases. For first one we should emit: "vmov.i8 d0, 0xff" For second one ("vmvn"): "vmov.i8 d0, 0x54" For last two instructions it should emit: "vmov.i8 d0, 0xab" P.S.: In ARMAsmParser.cpp I have also fixed few nearby style issues in old code. Just for keeping method bodies in harmony with themselves. llvm-svn: 207080
* Follow aliases when determining if a symbol is thumb.Rafael Espindola2014-04-221-1/+11
| | | | | | This fixes pr19484. llvm-svn: 206917
* Change the ARM assembler to require a :lower16: or :upper16 on non-constantKevin Enderby2014-04-184-7/+26
| | | | | | | | | | | | | | | | | | | | | | expressions for mov instructions instead of silently truncating by default. For the ARM assembler, we want to avoid misleadingly allowing something like "mov r0, <symbol>" especially when we turn it into a movw and the expression <symbol> does not have a :lower16: or :upper16" as part of the expression. We don't want the behavior of silently truncating, which can be unexpected and lead to bugs that are difficult to find since this is an easy mistake to make. This does change the previous behavior of llvm but actually matches an older gnu assembler that would not allow this but print less useful errors of like “invalid constant (0x927c0) after fixup” and “unsupported relocation on symbol foo”. The error for llvm is "immediate expression for mov requires :lower16: or :upper16" with correct location information on the operand as shown in the added test cases. rdar://12342160 llvm-svn: 206669
* Test commit - Added a new lineKonrad Anheim2014-04-161-0/+1
| | | | llvm-svn: 206399
* [MC] Emit an error if cfi_startproc is used before a symbol is defined.Quentin Colombet2014-04-151-0/+1
| | | | | | | | | Currently, we bind those directives with the last symbol, so if none has been defined, this would lead to a crash of the compiler. <rdar://problem/15939159> llvm-svn: 206236
* Don't lose the thumb bit by using relocations with sections.Rafael Espindola2014-04-111-1/+12
| | | | | | This fixes a regression from r205076. llvm-svn: 206047
* Remove the use of "%e" as it is not a valid expansion like "%t".Kaelyn Takata2014-04-101-2/+2
| | | | llvm-svn: 205991
* For the ARM integrated assembler add checking of theKevin Enderby2014-04-101-0/+8354
| | | | | | | | | | | | | | | | | | | alignments on vld/vst instructions. And report errors for alignments that are not supported. While this is a large diff and an big test case, the changes are very straight forward. But pretty much had to touch all vld/vst instructions changing the addrmode to one of the new ones that where added will do the proper checking for the specific instruction. FYI, re-committing this with a tweak so MemoryOp's default constructor is trivial and will work with MSVC 2012. Thanks to Reid Kleckner and Jim Grosbach for help with the tweak. rdar://11312406 llvm-svn: 205986
* Revert "For the ARM integrated assembler add checking of the alignments on ↵Reid Kleckner2014-04-101-8354/+0
| | | | | | | | | | | | | vld/vst instructions. And report errors for alignments that are not supported." It doesn't build with MSVC 2012, because MSVC doesn't allow union members that have non-trivial default constructors. This change added 'SMLoc AlignmentLoc' to MemoryOp, which made MemoryOp's default ctor non-trivial. This reverts commit r205930. llvm-svn: 205944
* For the ARM integrated assembler add checking of theKevin Enderby2014-04-091-0/+8354
| | | | | | | | | | | | | | | alignments on vld/vst instructions. And report errors for alignments that are not supported. While this is a large diff and an big test case, the changes are very straight forward. But pretty much had to touch all vld/vst instructions changing the addrmode to one of the new ones that where added will do the proper checking for the specific instruction. rdar://11312406 llvm-svn: 205930
* Fix the ARM VLD3 (single 3-element structure to all lanes)Kevin Enderby2014-04-081-1/+1
| | | | | | | | | | | | | | | size 16 double-spaced registers instruction printing. This: vld3.16 {d0[], d2[], d4[]}, [r4]! was being printed as: vld3.16 {d0[], d1[], d2[]}, [r4]! rdar://16531387 llvm-svn: 205779
* Fix for PR18921 (LDRD/STRD part)::Stepan Dyatkovskiy2014-04-044-0/+59
| | | | | | | | Removed "GNU Assembler extension (compatibility)" definitions from ARMInstrInfo.td Fixed ARMAsmParser::ParseInstruction GNU compatability branch, so it also works for thumb mode from now. Added new tests. llvm-svn: 205622
* Fixed register class in STRD instruction for Thumb2 mode.Stepan Dyatkovskiy2014-04-042-0/+16
| | | | llvm-svn: 205612
* ARM: update even more testsSaleem Abdulrasool2014-04-032-12/+34
| | | | | | | | | More updating of tests to be explicit about the target triple rather than relying on the default target triple supporting ARM mode. Indicate to lit that object emission is not yet available for Windows on ARM. llvm-svn: 205545
* ARM: fixup more tests to specify the target more explicitlySaleem Abdulrasool2014-04-033-7/+15
| | | | | | | | | | | | | This changes the tests that were targeting ARM EABI to explicitly specify the environment rather than relying on the default. This breaks with the new Windows on ARM support when running the tests on Windows where the default environment is no longer EABI. Take the opportunity to avoid a pointless redirect (helps when trying to debug with providing a command line invocation which can be copy and pasted) and removing a few greps in favour of FileCheck. llvm-svn: 205541
* PR19320:Stepan Dyatkovskiy2014-04-031-0/+9
| | | | | | | The trouble as in ARMAsmParser, in ParseInstruction method. It assumes that ARM::R12 + 1 == ARM::SP. It is wrong, since ARM::<Register> codes are generated by tablegen and actually could be any random numbers. llvm-svn: 205524
* Recommitted fix for PR18931, with extended tests set.Stepan Dyatkovskiy2014-03-295-8/+32
| | | | | | | | | | | | | Issue subject: Crash using integrated assembler with immediate arithmetic Fix description: Expressions like 'cmp r0, #(l1 - l2) >> 3' could not be evaluated on asm parsing stage, since it is impossible to resolve labels on this stage. In the end of stage we still have expression (MCExpr). Then, when we want to encode it, we expect it to be an immediate, but it still an expression. Patch introduces a Fixup (MCFixup instance), that is processed after main encoding stage. llvm-svn: 205094
* Completely rewrite ELFObjectWriter::RecordRelocation.Rafael Espindola2014-03-291-21/+12
| | | | | | | | | | | | | | | | | | | I started trying to fix a small issue, but this code has seen a small fix too many. The old code was fairly convoluted. Some of the issues it had: * It failed to check if a symbol difference was in the some section when converting a relocation to pcrel. * It failed to check if the relocation was already pcrel. * The pcrel value computation was wrong in some cases (relocation-pc.s) * It was missing quiet a few cases where it should not convert symbol relocations to section relocations, leaving the backends to patch it up. * It would not propagate the fact that it had changed a relocation to pcrel, requiring a quiet nasty work around in ARM. * It was missing comments. llvm-svn: 205076
* Add ARM big endian Target (armeb, thumbeb)Christian Pirker2014-03-284-14/+77
| | | | | | Reviewed at http://llvm-reviews.chandlerc.com/D3095 llvm-svn: 205007
* Rejected r204899 and r204900 due to remaining test failures on ↵Stepan Dyatkovskiy2014-03-271-9/+0
| | | | | | cmake-llvm-x86_64-linux buildbot. llvm-svn: 204901
* Fixed test for r204899 (pr18931 fix)Stepan Dyatkovskiy2014-03-271-2/+2
| | | | llvm-svn: 204900
* Fix for pr18931: Crash using integrated assembler with immediate arithmeticStepan Dyatkovskiy2014-03-271-0/+9
| | | | | | | | | | | Fix description: Expressions like 'cmp r0, #(l1 - l2) >> 3' could not be evaluated on asm parsing stage, since it is impossible to resolve labels on this stage. In the end of stage we still have expression (MCExpr). Then, when we want to encode it, we expect it to be an immediate, but it still an expression. Patch introduces a Fixup (MCFixup instance), that is processed after main encoding stage. llvm-svn: 204899
* ARM: raise error message when complex SO expressions can't really beJiangning Liu2014-03-271-0/+8
| | | | | | solved as a constant at compilation time. llvm-svn: 204898
* Fix the ARM VST4 (single 4-element structure from one lane)Kevin Enderby2014-03-261-1/+1
| | | | | | | | | | | | | | | size 16 double-spaced registers instruction printing. This: vld4.16 {d17[1], d19[1], d21[1], d23[1]}, [r7]! was being printed as: vld4.16 {d17[1], d18[1], d19[1], d20[1]}, [r7]! rdar://16435096 llvm-svn: 204847
* Teach llvm-readobj to print human friendly description of reserved sections.Rafael Espindola2014-03-241-2/+2
| | | | llvm-svn: 204584
* ARM IAS: properly handle function entries in .thumbSaleem Abdulrasool2014-03-222-2/+83
| | | | | | | | | | | | | | | | | | | | When a label is parsed, check if there is type information available for the label. If so, check if the symbol is a function. If the symbol is a function and we are in thumb mode and no explicit thumb_func has been emitted, adjust the symbol data to indicate that the function definition is a thumb function. The application of this inferencing is improved value handling in the object file (the required thumb bit is set on symbols which are thumb functions). It also helps improve compatibility with binutils. The one complication that arises from this handling is the MCAsmStreamer. The default implementation of getOrCreateSymbolData in MCStreamer does not support tracking the symbol data. In order to support the semantics of thumb functions, track symbol data in assembly streamer. Although O(n) in number of labels in the TU, this is already done in various other streamers and as such the memory overhead is not a practical concern in this scenario. llvm-svn: 204544
* This reverts commit r203762, "ARM: support emission of complex SO expressions".Jiangning Liu2014-03-211-9/+0
| | | | | | The commit r203762 introduced silent failure for complext SO expression, and it's even worse than compiler crash. llvm-svn: 204427
* llvm-objdump output hex to match binutils' objdumpGreg Fitzgerald2014-03-202-26/+26
| | | | | | Patch by Ted Woodward llvm-svn: 204409
* Reapply 'ARM IAS: support .thumb_set'Saleem Abdulrasool2014-03-202-0/+183
| | | | | | | Re-apply the change after it was reverted to do conflicts due to another change being reverted. llvm-svn: 204306
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