summaryrefslogtreecommitdiffstats
path: root/llvm/test/MC/ARM/v8_IT_manual.s
Commit message (Collapse)AuthorAgeFilesLines
* [ARM] Make coprocessor number restrictions consistent.Simon Tatham2019-06-271-464/+464
| | | | | | | | | | | | | | | | | | | | | | Different versions of the Arm architecture disallow the use of generic coprocessor instructions like MCR and CDP on different sets of coprocessors. This commit centralises the check of the coprocessor number so that it's consistent between assembly and disassembly, and also updates it for the new restrictions in Arm v8.1-M. New tests added that check all the coprocessor numbers; old tests updated, where they used a number that's now become illegal in the context in question. Reviewers: DavidSpickett, ostannard Subscribers: javed.absar, kristof.beyls, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D63863 llvm-svn: 364532
* [ARM] Add missing Thumb2 assembler diagnostics.Eli Friedman2018-06-281-15/+0
| | | | | | | | | | Mostly just adding checks for Thumb2 instructions which correspond to ARM instructions which already had diagnostics. While I'm here, also fix ARM-mode strd to check the input registers correctly. Differential Revision: https://reviews.llvm.org/D48610 llvm-svn: 335909
* [ARM] Tighten up CHECK lines in a testOliver Stannard2017-10-241-2184/+2184
| | | | | | | | | | | | | These tests checked for the line number without a leading ":", so for example, a missed diagnostic on line 123 could match one on line 1123, 2123, etc, desynchronising the test for hundreds of lines. This couldn't cause it to incorrectly pass or fail, but made it hard to track down test failures. Differential revision: https://reviews.llvm.org/D39238 llvm-svn: 316442
* ARM: improve instruction validation for thumb modeSaleem Abdulrasool2014-12-181-3/+4
| | | | | | | | | | | | | | | | | | | | | | | | | The ARM Architecture Reference Manual states the following: LDM{,IA,DB}: The SP cannot be in the list. The PC can be in the list. If the PC is in the list: • the LR must not be in the list • the instruction must be either outside any IT block, or the last instruction in an IT block. POP: The PC can be in the list. If the PC is in the list: • the LR must not be in the list • the instruction must be either outside any IT block, or the last instruction in an IT block. PUSH: The SP and PC can be in the list in ARM instructions, but not in Thumb instructions. STM:{,IA,DB}: The SP and PC can be in the list in ARM instructions, but not in Thumb instructions. llvm-svn: 224502
* Revert "[Thumb/Thumb2] Added restrictions on PC, LR, SP in the register list ↵Rafael Espindola2014-12-041-4/+3
| | | | | | | | | | for PUSH/POP/LDM/STM. <Differential Revision: http://reviews.llvm.org/D6090>" This reverts commit r223356. It was failing check-all (MC/ARM/thumb.s in particular). llvm-svn: 223363
* [Thumb/Thumb2] Added restrictions on PC, LR, SP in the register list for ↵Jyoti Allur2014-12-041-3/+4
| | | | | | PUSH/POP/LDM/STM. <Differential Revision: http://reviews.llvm.org/D6090> llvm-svn: 223356
* [ARM] Handling for coprocessor instructions that are undefined starting from ↵Artyom Skrobov2013-11-081-2992/+16
| | | | | | ARMv8 (Thumb encodings) llvm-svn: 194263
* [ARM] Warn on deprecated IT blocks in v8 AArch32 assembly.Amara Emerson2013-10-031-0/+9715
Patch by Artyom Skrobov. llvm-svn: 191885
OpenPOWER on IntegriCloud