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* Revert "[ARM] Fix assembly and disassembly for VMRS/VMSR"Tim Northover2017-08-081-0/+16
| | | | | | | | This reverts r310243. Only MVFR2 is actually restricted to v8 and it'll be a little while before we can get a proper fix together. Better that we allow incorrect code than reject correct in the meantime. llvm-svn: 310384
* [ARM] Fix assembly and disassembly for VMRS/VMSRAndre Vieira2017-08-071-16/+0
| | | | | | | | | | | | | | | | This patch addresses two issues with assembly and disassembly for VMRS/VMSR: 1.currently VMRS/VMSR instructions accessing fpsid, mvfr{0-2} and fpexc, are accepted for non ARMv8-A targets. 2. all VMRS/VMSR instructions accept writing/reading to PC and SP, when only ARMv7-A and ARMv8-A should be allowed to write/read to SP and none to PC. This patch addresses those issues and adds tests for these cases. Differential Revision: https://reviews.llvm.org/D36306 llvm-svn: 310243
* [ARM] remove FIXMEs and add vcmp MC testSjoerd Meijer2017-03-091-0/+12
| | | | | | | | | Minor cleanup in ARMInstrVFP.td: removed some FIXMEs and added a MC test for vcmp that was actually missing. Differential Revision: https://reviews.llvm.org/D30745 llvm-svn: 297376
* Add ARM fconsts/fconstd aliases for vmov.f32/vmov.f64David Peixotto2014-01-071-0/+43
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit adds the pre-UAL aliases of fconsts and fconstd for vmov.f32 and vmov.f64. They use an InstAlias rather than a MnemonicAlias to properly support the predicate operand. We need to support encoded 8-bit constants in order to implement the pre-UAL fconsts/fconstd aliases for vmov.f32/vmov.f64, so this commit also fixes parsing of encoded floating point constants used in vmov.f32/vmov.f64 instructions. Now we can support assembly code like this: fconsts s0, #0x70 which is equivalent to vmov.f32 s0, #1.0. Most of the code was already in place to support this feature. Previously the code was trying to accept encoded 8-bit float constants for the vmov.f32/vmov.f64 instructions. It looks like the support for parsing encoded floats was lost in a refactoring in commit r148556 and we did not have any tests in place to catch it. The change in this commit is to keep the parsed value as a 32-bit float instead of a 64-bit double because that is what the isFPImm() function expects to find. There is no loss of precision by using a 32-bit float here because we are still limited to an 8-bit encoded value in the end. Additionally, we explicitly reject encoded 8-bit floats for vmovf.32/64. This is the same as the current behavior, but we now do it explicitly rather than accidently. llvm-svn: 198697
* This patch adds support for FPINST/FPINST2 as operands to vmsr/vmrs. These ↵Mihai Popa2013-06-111-0/+8
| | | | | | are optional registers that may be supported some ARM implementations to aid with resolution of floating point exceptions. The manual pages for vmsr and vmrs do not detail their use. Encodings and other information can be found in ARM Architecture Reference Manual section F, chapter 6, paragraph 3. llvm-svn: 183733
* ARM: add fstmx and fldmx instructions for assemblyTim Northover2013-05-311-0/+14
| | | | | | | | | These instructions are deprecated oddities, but we still need to be able to disassemble (and reassemble) them if and when they're encountered. Patch by Amaury de la Vieuville. llvm-svn: 183011
* Fix instruction description of VMOV (between two ARM core registers and two ↵Richard Barton2012-07-101-0/+21
| | | | | | single-precision resiters) (and do it properly this time! llvm-svn: 159989
* Revert r159938 (and r159945) to appease the buildbots.Chad Rosier2012-07-091-21/+0
| | | | llvm-svn: 159960
* Fix instruction description of VMOV (between two ARM core registers and two ↵Richard Barton2012-07-091-0/+21
| | | | | | single-precision resiters) llvm-svn: 159938
* ARM some VFP tblgen'erated two-operand aliases.Jim Grosbach2012-04-201-2/+7
| | | | llvm-svn: 155178
* Tidy up. Formatting.Jim Grosbach2012-04-201-53/+45
| | | | llvm-svn: 155177
* ARM vmrs system registers mvfr0 and mvfr1 handling.Jim Grosbach2012-03-161-3/+12
| | | | | | rdar://11058464 llvm-svn: 152881
* ARM case-insensitive checking for APSR_nzcv.Jim Grosbach2012-03-151-2/+4
| | | | | | rdar://11056591 llvm-svn: 152846
* Fix VCVT decoding (between floating-point and fixed-point, Floating-point). ↵Kristof Beyls2012-03-151-1/+26
| | | | | | Patch by Richard Barton. llvm-svn: 152814
* NEON use vmov.i32 to splat some f32 values into vectors.Jim Grosbach2012-01-201-0/+8
| | | | | | | | | | | For bit patterns that aren't representable using the 8-bit floating point representation for vmov.f32, but are representable via vmov.i32, treat the .f32 syntax as an alias. Most importantly, this covers the case 'vmov.f32 Vd, #0.0'. rdar://10616677 llvm-svn: 148556
* ARM VFP assembly parsing and encoding for VCVT(float <--> fixed point).Jim Grosbach2011-12-221-0/+12
| | | | | | rdar://10558523 llvm-svn: 147189
* ARM VFP optional data type on VMOV GPR<-->SPR.Jim Grosbach2011-12-211-0/+28
| | | | llvm-svn: 147104
* ARM assembly parsing for optional datatype suffix on VFP VMOV GPR<->VFP insns.Jim Grosbach2011-11-151-0/+10
| | | | | | Yet more of rdar://10435076. llvm-svn: 144691
* ARM assembly parsing for two-operand form of 'mul' instruction.Jim Grosbach2011-11-151-0/+6
| | | | | | rdar://10449856. llvm-svn: 144689
* ARM VLDR/VSTR instructions don't need a size suffix.Jim Grosbach2011-11-141-27/+27
| | | | | | | Canonicallize on the non-suffixed form, but continue to accept assembly that has any correctly sized type suffix. llvm-svn: 144583
* ARM optional size suffix for VLDR/VSTR syntax.Jim Grosbach2011-11-111-0/+10
| | | | llvm-svn: 144427
* ARM allow Q registers in vldm/vstm register lists.Jim Grosbach2011-11-111-0/+2
| | | | | | rdar://9672822 llvm-svn: 144407
* ARM assembly parsing and encoding for VMOV immediate.Jim Grosbach2011-10-031-5/+9
| | | | llvm-svn: 141046
* ARM parsing/encoding for VCMP/VCMPE.Jim Grosbach2011-10-031-4/+4
| | | | llvm-svn: 141038
* ARM assembly parsing and encoding for VMRS/FMSTAT.Jim Grosbach2011-10-031-2/+4
| | | | llvm-svn: 141025
* Add missing encoding information for some of the GPR<->FP register moves.Owen Anderson2011-08-291-0/+3
| | | | llvm-svn: 138780
* Improve handling of #-0 offsets for many more pre-indexed addressing modes.Owen Anderson2011-08-291-7/+7
| | | | llvm-svn: 138754
* Do AsmMatcher operand classification per-opcode.Jim Grosbach2011-02-101-1/+0
| | | | | | | | | | When matching operands for a candidate opcode match in the auto-generated AsmMatcher, check each operand against the expected operand match class. Previously, operands were classified independently of the opcode being handled, which led to difficulties when operand match classes were more complicated than simple subclass relationships. llvm-svn: 125245
* Add encoding testcases for ARM vcvtr variationsBruno Cardoso Lopes2011-01-261-0/+9
| | | | llvm-svn: 124289
* When matching asm operands, always try to match the most restricted type first.Owen Anderson2011-01-181-0/+1
| | | | | | | | | | | | Unfortunately, while this is the "right" thing to do, it breaks some ARM asm parsing tests because MemMode5 and ThumbMemModeReg are ambiguous. This is tricky to resolve since neither is a subset of the other. XFAIL the test for now. The old way was broken in other ways, just ways we didn't happen to be testing, and our ARM asm parsing is going to require significant revisiting at a later point anyways. llvm-svn: 123786
* Create two new generic classes to represent the following VMRS/VMSR variations:Bruno Cardoso Lopes2011-01-181-0/+8
| | | | | | | | | vmrs reg, fpexc vmrs reg, fpsid vmsr fpexc, reg vmsr fpsid, reg llvm-svn: 123783
* Proper encoding for VLDM and VSTM instructions. The register lists for theseBill Wendling2010-11-171-0/+10
| | | | | | | | | instructions have to distinguish between lists of single- and double-precision registers in order for the ASM matcher to do a proper job. In all other respects, a list of single- or double-precision registers are the same as a list of GPR registers. llvm-svn: 119460
* Add encoding for VSTR.Bill Wendling2010-11-041-0/+14
| | | | llvm-svn: 118220
* The MC code couldn't handle ARM LDR instructions with negative offsets:Bill Wendling2010-11-031-1/+20
| | | | | | | | | | | | vldr.64 d1, [r0, #-32] The problem was with how the addressing mode 5 encodes the offsets. This change makes sure that the way offsets are handled in addressing mode 5 is consistent throughout the MC code. It involves re-refactoring the "getAddrModeImmOpValue" method into an "Imm12" and "addressing mode 5" version. But not to worry! The majority of the duplicated code has been unified. llvm-svn: 118144
* Rename getAddrModeImm12OpValue to getAddrModeImmOpValue and expand it to workBill Wendling2010-11-021-0/+17
| | | | | | | | with immediates up to 16-bits in size. The same logic is applied to other LDR encodings, e.g. VLDR, but which use a different immediate bit width (8-bits in VLDR's case). Removing the "12" allows it to be more generic. llvm-svn: 118094
* Use ARM-style comments.Bill Wendling2010-11-011-62/+61
| | | | llvm-svn: 117955
* Mark ARM subtarget features that are available for the assembler.Jim Grosbach2010-11-011-1/+1
| | | | llvm-svn: 117929
* Some instructions end with an "ls" prefix, but it doesn't indicate that they areBill Wendling2010-10-291-0/+160
conditional. Check for those instructions explicitly. llvm-svn: 117747
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