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* ARM 'vuzp.32 Dd, Dm' is a pseudo-instruction.Jim Grosbach2012-04-111-0/+2
| | | | | | | | | | While there is an encoding for it in VUZP, the result of that is undefined, so we should avoid it. Define the instruction as a pseudo for VTRN.32 instead, as the ARM ARM indicates. rdar://11222366 llvm-svn: 154511
* ARM 'vzip.32 Dd, Dm' is a pseudo-instruction.Jim Grosbach2012-04-111-0/+2
| | | | | | | | | | While there is an encoding for it in VZIP, the result of that is undefined, so we should avoid it. Define the instruction as a pseudo for VTRN.32 instead, as the ARM ARM indicates. rdar://11221911 llvm-svn: 154505
* ARM 64-bit VEXT assembly uses a .64 suffix, not .32, amazingly enough.Jim Grosbach2011-12-081-0/+4
| | | | llvm-svn: 146194
* ARM optional destination operand variants for VEXT instructions.Jim Grosbach2011-12-081-0/+15
| | | | llvm-svn: 146114
* Tidy up.Jim Grosbach2011-12-081-22/+29
| | | | llvm-svn: 146113
* ARM alternate size suffices for VTRN instructions.Jim Grosbach2011-11-151-0/+60
| | | | | | rdar://10435076 llvm-svn: 144694
* Fix misspelled target triples in MC/ARM test commands.Bob Wilson2010-12-151-1/+1
| | | | llvm-svn: 121901
* Unlike a lot of NEON instructions, vext isn't _actually_ parameterized by ↵Owen Anderson2010-11-031-2/+2
| | | | | | | | | element size. Instead, all of the different element sizes are pseudo instructions that map down to vext.8 underneath, with the immediate shifted left to reflect the increased element size. llvm-svn: 118183
* Covert this test to .s form.Owen Anderson2010-11-011-0/+46
llvm-svn: 117937
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