summaryrefslogtreecommitdiffstats
path: root/llvm/test/MC/ARM/ldr-pseudo.s
Commit message (Collapse)AuthorAgeFilesLines
* Re-apply r286006: Fix 24560: assembler does not share constant pool for ↵James Molloy2017-05-221-3/+1
| | | | | | | | | | | | | | | | | same constants Re-applying now that the open bug on this commit, PR32825, is known to be fixed. Original commit message: Summary: This patch returns the same label if the CP entry with the same value has been created. Reviewers: eli.friedman, rengolin, jmolloy Subscribers: majnemer, jmolloy, llvm-commits Differential Revision: https://reviews.llvm.org/D25804 llvm-svn: 303539
* Revert "Fix 24560: assembler does not share constant pool for same constants"James Molloy2017-05-221-1/+3
| | | | | | This reverts commit r286006. It caused PR32825 and wasn't fixed. llvm-svn: 303535
* Fix 24560: assembler does not share constant pool for same constantsWeiming Zhao2016-11-041-3/+1
| | | | | | | | | | | | Summary: This patch returns the same label if the CP entry with the same value has been created. Reviewers: eli.friedman, rengolin, jmolloy Subscribers: majnemer, jmolloy, llvm-commits Differential Revision: https://reviews.llvm.org/D25804 llvm-svn: 286006
* [ARM] Support and tests for transform of LDR rt, = to MOVRenato Golin2016-05-121-4/+97
| | | | | | | | | | | | | | | | | | | | | | | | | | This change implements the transformation in processInstruction() for the LDR rt, =expression to MOV rt, expression when the expression can be evaluated and can fit into the immediate field of the MOV or a MVN. Across the ARM and Thumb instruction sets there are several cases to consider, each with a different range of representatble constants. In ARM we have: * Modified immediate (All ARM architectures) * MOVW (v6t2 and above) In Thumb we have: * Modified immediate (v6t2, v7m and v8m.mainline) * MOVW (v6t2, v7m, v8.mainline and v8m.baseline) * Narrow Thumb MOV that can be used in an IT block (non flag-setting) If the immediate fits any of the available alternatives then we make the transformation. Fixes 25722. Patch by Peter Smith. llvm-svn: 269354
* [ARM] Fixup tests to take into account mov translation. NFC.Renato Golin2016-05-121-16/+16
| | | | | | | | | | | | | Alter instances in the test-suite that use immediates that can be represented in the immediate field of a MOV. The reason for doing this is that when the LDR rt,=imm transformation to MOV rt, imm the existing tests do not need to be modified. Required by the patch that fixes PR25722. Patch by Peter Smith. llvm-svn: 269353
* Followup to 258750; update all MC tests to use .p2align .Dan Gohman2016-01-261-10/+10
| | | | llvm-svn: 258754
* Generalise assembly tests to not rely on anonymous symbol namesOliver Stannard2014-03-141-32/+32
| | | | llvm-svn: 203909
* Implement the ldr-pseudo opcode for ARM assemblyDavid Peixotto2013-12-191-0/+221
The ldr-pseudo opcode is a convenience for loading 32-bit constants. It is converted into a pc-relative load from a constant pool. For example, ldr r0, =0x10001 ldr r1, =bar will generate this output in the final assembly ldr r0, .Ltmp0 ldr r1, .Ltmp1 ... .Ltmp0: .long 0x10001 .Ltmp1: .long bar Sketch of the LDR pseudo implementation: Keep a map from Section => ConstantPool When parsing ldr r0, =val parse val as an MCExpr get ConstantPool for current Section Label = CreateTempSymbol() remember val in ConstantPool at next free slot add operand to ldr that is MCSymbolRef of Label On finishParse() callback Write out all non-empty constant pools for each Entry in ConstantPool Emit Entry.Label Emit Entry.Value Possible improvements to be added in a later patch: 1. Does not convert load of small constants to mov (e.g. ldr r0, =0x1 => mov r0, 0x1) 2. Does reuse constant pool entries for same constant The implementation was tested for ARM, Thumb1, and Thumb2 targets on linux and darwin. llvm-svn: 197708
OpenPOWER on IntegriCloud