| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | [ARM][v8.5A] Add speculation barriers SSBB and PSSBB | Oliver Stannard | 2018-09-28 | 1 | -2/+2 |
| * | [ARM] Enable the use of SVC anywhere in an IT block | Andre Vieira | 2017-09-11 | 1 | -0/+6 |
| * | [ARM] Add .w aliases of MOV with shifted operand | John Brawn | 2017-06-22 | 1 | -0/+16 |
| * | [ARM] Diagnose PC-writing instructions in IT blocks | Oliver Stannard | 2017-02-28 | 1 | -2/+4 |
| * | [ARM] LSL #0 is an alias of MOV | John Brawn | 2017-02-27 | 1 | -0/+27 |
| * | [ARM] Thumb2 LDR (literal) should accept PC as the destination | Oliver Stannard | 2016-11-10 | 1 | -0/+5 |
| * | [ARM] Operands for PKHTB alias should be swapped | Oliver Stannard | 2016-01-18 | 1 | -1/+1 |
| * | [ARM] Small refactor of tryConvertingToTwoOperandForm (nfc) | Scott Douglass | 2015-07-13 | 1 | -3/+77 |
| * | Fixed register class in STRD instruction for Thumb2 mode. | Stepan Dyatkovskiy | 2014-04-04 | 1 | -0/+6 |
| * | Add ARM big endian Target (armeb, thumbeb) | Christian Pirker | 2014-03-28 | 1 | -5/+28 |
| * | Tidy up a bit. Formatting only. | Jim Grosbach | 2014-02-11 | 1 | -8/+8 |
| * | ARM: Thumb2 LDR(literal) can target SP. | Jim Grosbach | 2014-02-11 | 1 | -0/+5 |
| * | [ARM] In ARMAsmParser, MatchCoprocessorOperandName() permitted p10 and p11 as... | Artyom Skrobov | 2013-11-08 | 1 | -12/+12 |
| * | Return early from getUnconditionalBranchTargetOpValue if the branch target is | Lang Hames | 2013-10-28 | 1 | -2/+2 |
| * | Make ARM hint ranges consistent, and add tests for these ranges | Artyom Skrobov | 2013-10-23 | 1 | -0/+10 |
| * | Add hint disassembly syntax for 16-bit Thumb hint instructions. | Richard Barton | 2013-10-18 | 1 | -0/+17 |
| * | Make "mov" work for all Thumb2 MOV encodings | Mihai Popa | 2013-08-21 | 1 | -1/+16 |
| * | Thumb2 add immediate alias for SP | Mihai Popa | 2013-08-19 | 1 | -0/+2 |
| * | Add support for Thumb2 literal loads with negative zero offset | Mihai Popa | 2013-08-16 | 1 | -0/+12 |
| * | Fix Thumb2 aliasing complementary instructions taking modified immediates | Mihai Popa | 2013-08-16 | 1 | -1/+8 |
| * | This fixes three issues related to Thumb literal loads: | Mihai Popa | 2013-08-15 | 1 | -4/+12 |
| * | This fixes the Thumb2 CPS assembly syntax. | Mihai Popa | 2013-08-09 | 1 | -0/+25 |
| * | Fix assembling of Thumb2 branch instructions. | Mihai Popa | 2013-08-09 | 1 | -2/+2 |
| * | Support APSR_nzcv as operand for Thumb2 mrc. Deprecate pre-UAL syntax (pc ins... | Mihai Popa | 2013-08-06 | 1 | -9/+12 |
| * | Added the B9.3.19 SUBS PC, LR, #imm (Thumb2) system instruction. | Kevin Enderby | 2013-07-31 | 1 | -0/+4 |
| * | This adds range checking for "ldr Rn, [pc, #imm]" Thumb | Mihai Popa | 2013-07-22 | 1 | -2/+19 |
| * | ARM: Add instruction aliases for the Thumb2 PLD/PLDW (literal) alternate form. | Tilmann Scheller | 2013-07-19 | 1 | -0/+3 |
| * | ARM: Add support for the Thumb2 PLI alternate literal form. | Tilmann Scheller | 2013-07-16 | 1 | -0/+4 |
| * | ARM: Prevent ARMAsmParser::shouldOmitCCOutOperand() from misidentifying certa... | Tilmann Scheller | 2013-07-03 | 1 | -0/+2 |
| * | This corrects the implementation of Thumb ADR instruction. There are three i... | Mihai Popa | 2013-07-03 | 1 | -3/+5 |
| * | [ARMAsmParser] Sort the ARM register lists based on the encoding value, not the | Chad Rosier | 2013-07-01 | 1 | -1/+1 |
| * | ARM: Fix pseudo-instructions for SRS (Store Return State). | Tilmann Scheller | 2013-06-28 | 1 | -6/+6 |
| * | ARM: fix literal load with positive offset encoding | Amaury de la Vieuville | 2013-06-18 | 1 | -1/+20 |
| * | ARM: fix t2am_imm8_offset operand printing for imm=#-0 | Amaury de la Vieuville | 2013-06-13 | 1 | -0/+2 |
| * | ARM: ISB cannot be passed the same options as DMB | Amaury de la Vieuville | 2013-06-10 | 1 | -0/+4 |
| * | ARM: Fix encoding of hint instruction for Thumb. | Quentin Colombet | 2013-04-26 | 1 | -4/+0 |
| * | ARM: Convenience aliases for 'srs*' instructions. | Jim Grosbach | 2013-02-23 | 1 | -0/+26 |
| * | Make sure the alternate PC+imm syntax of LDR instruction with a small | Kevin Enderby | 2012-12-14 | 1 | -0/+4 |
| * | Fix #13035, a bug around Thumb instruction LDRD/STRD with negative #0 offset ... | Jiangning Liu | 2012-08-02 | 1 | -0/+12 |
| * | Fix #13138, a bug around ARM instruction DSB encoding and decoding issue. | Jiangning Liu | 2012-08-02 | 1 | -0/+68 |
| * | Fix #13241, a bug around shift immediate operand for ARM instruction ADR. | Jiangning Liu | 2012-08-02 | 1 | -0/+2 |
| * | ARM: Define generic HINT instruction. | Jim Grosbach | 2012-06-18 | 1 | -1/+15 |
| * | ARM: Add a few missing add->sub aliases w/ 'w' suffix. | Jim Grosbach | 2012-05-01 | 1 | -0/+12 |
| * | ARM: Thumb add(sp plus register) asm constraints. | Jim Grosbach | 2012-04-27 | 1 | -0/+2 |
| * | Fix ARM assembly parsing for upper case condition codes on IT instructions. | Richard Barton | 2012-04-27 | 1 | -0/+13 |
| * | Specify cpu to unbreak tests. | Evan Cheng | 2012-04-26 | 1 | -1/+1 |
| * | ARM fix cc_out operand handling for t2SUBrr instructions. | Jim Grosbach | 2012-04-10 | 1 | -0/+12 |
| * | ARM assembly parsing for 'msr' plain 'cpsr' operand. | Jim Grosbach | 2012-04-05 | 1 | -0/+2 |
| * | ARM assembler should prefer non-aliases encoding of cmp. | Jim Grosbach | 2012-03-30 | 1 | -2/+5 |
| * | ARM integrated assembler should encoding choice for add/sub imm. | Jim Grosbach | 2012-03-30 | 1 | -0/+8 |
