summaryrefslogtreecommitdiffstats
path: root/llvm/test/MC/ARM/arm_instructions.s
Commit message (Collapse)AuthorAgeFilesLines
* Remove the cortex-a9-mp CPU.Charlie Turner2014-11-031-1/+1
| | | | | | | | | | | | | | | | | | This CPU definition is redundant. The Cortex-A9 is defined as supporting multiprocessing extensions. Remove its definition and update appropriate tests. LLVM defines both a cortex-a9 CPU and a cortex-a9-mp CPU. The only difference between the two CPU definitions in ARM.td is that cortex-a9-mp contains the feature FeatureMP for multiprocessing extensions. This is redundant since the Cortex-A9 is defined as having multiprocessing extensions in the TRMs. armcc also defines the Cortex-A9 as having multiprocessing extensions by default. Change-Id: Ifcadaa6c322be0a33d9d2a39cfdd7da1d75981a7 llvm-svn: 221166
* Add a special ARM trap encoding for NaCl.Eli Bendersky2013-01-301-4/+11
| | | | | | | | More details in this thread: http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20130128/163783.html Patch by JF Bastien llvm-svn: 173943
* Fixed the LLVM ARM v7 assembler and instruction printer for 8-bit immediate ↵Silviu Baranga2012-05-111-0/+3
| | | | | | offset addressing. The assembler and instruction printer were not properly handeling the #-0 immediate. llvm-svn: 156608
* Support a valid, but not very useful, encoding of CPSIE where none of the ↵Owen Anderson2011-10-051-0/+3
| | | | | | AIF bits are set. llvm-svn: 141190
* ARM update tests for CPS instruction.Jim Grosbach2011-07-291-9/+0
| | | | llvm-svn: 136472
* Update ARM tests for parsing and encoding of WFE, WFI and YIELD.Jim Grosbach2011-07-281-9/+0
| | | | llvm-svn: 136358
* ARM parsing and encoding tests for load/store exclusive instructions.Jim Grosbach2011-07-261-24/+0
| | | | llvm-svn: 136105
* ARM parsing and encoding tests for SBC instruction.Jim Grosbach2011-07-211-3/+0
| | | | llvm-svn: 135718
* ARM assembly parsing support for RSC instruction.Jim Grosbach2011-07-211-3/+0
| | | | | | | Add two-operand instruction aliases. Add parsing and encoding tests for variants of the instruction. llvm-svn: 135713
* ARM assembly parsing support for RSB instruction.Jim Grosbach2011-07-211-3/+0
| | | | | | | Add two-operand instruction aliases. Add parsing and encoding tests for variants of the instruction. llvm-svn: 135712
* ARM parsing and encodings tests for saturating arithmetic insns.Jim Grosbach2011-07-211-12/+0
| | | | llvm-svn: 135709
* Add parsing/encoding tests for ARM ORR instruction.Jim Grosbach2011-07-201-6/+0
| | | | llvm-svn: 135602
* Consolidate ARM NOP encoding test.Jim Grosbach2011-07-201-11/+0
| | | | llvm-svn: 135600
* Tweak ARM assembly parsing and printing of MSR instruction.Jim Grosbach2011-07-191-39/+0
| | | | | | | | The system register spec should be case insensitive. The preferred form for output with mask values of 4, 8, and 12 references APSR rather than CPSR. Update and tidy up tests accordingly. llvm-svn: 135532
* ARM assembly parsing of MRS instruction.Jim Grosbach2011-07-191-3/+0
| | | | | | | Teach the parser to recognize the APSR and SPSR system register names. Add and update tests accordingly. llvm-svn: 135527
* Move mr[r]c[2] ARM tests and tidy up a bit.Jim Grosbach2011-07-191-10/+0
| | | | llvm-svn: 135517
* Add some testcases for ARM MLA/MLS instructions.Jim Grosbach2011-07-141-3/+0
| | | | llvm-svn: 135196
* ARM MCRR/MCRR2 immediate operand range checking.Jim Grosbach2011-07-141-4/+0
| | | | llvm-svn: 135192
* ARM MCR/MCR2 assembly parsing operand constraints.Jim Grosbach2011-07-141-4/+0
| | | | | | | The immediate operands are restricted to 0-7. Enforce that when parsing assembly. llvm-svn: 135189
* Enable some tests we now handle correctly.Jim Grosbach2011-07-141-18/+9
| | | | llvm-svn: 135185
* Update ARM Assembly of LDM/STM.Jim Grosbach2011-07-141-44/+0
| | | | | | | ldm/stm are the cannonical spellings for ldmia/stmia, so use them as such. Update the parsing/encoding tests accordingly. llvm-svn: 135168
* ARM ISB assembly parsing tests.Jim Grosbach2011-07-141-2/+0
| | | | llvm-svn: 135158
* ARM ISB instruction assembly parsing.Jim Grosbach2011-07-141-1/+1
| | | | | | | The ISB instruction takes an optional operand, just like DMB/DSB. Typically only 'sy' is meaningful. llvm-svn: 135156
* Remove duplicate tests.Jim Grosbach2011-07-141-24/+0
| | | | llvm-svn: 135117
* ARM Assembler support for DMB instruction.Jim Grosbach2011-07-131-24/+0
| | | | | | | | Flesh out the options supported for the instruction. Shuffle tests a bit and add entries for the rest of the options. Add an alias to handle the default operand of "sy". llvm-svn: 135109
* Shuffle ARM assembly tests a bit.Jim Grosbach2011-07-131-6/+0
| | | | llvm-svn: 135095
* ARM assembler support for ldmfd/stmfd mnemonics.Jim Grosbach2011-06-271-0/+8
| | | | llvm-svn: 133936
* Fix ssat and ssat16 encodings for ARM and Thumb. The bit position valueBruno Cardoso Lopes2011-05-311-0/+3
| | | | | | | must be encoded decremented by one. Only add encoding tests for ssat16 because ssat can't be parsed yet. llvm-svn: 132324
* Fix PR9762Bruno Cardoso Lopes2011-05-251-0/+3
| | | | | | Enable the parsing of the operand "cpsr_all" for the ARM msr instruction llvm-svn: 132026
* Add asm parsing support w/ testcases for strex/ldrex family of instructionsBruno Cardoso Lopes2011-03-241-0/+25
| | | | llvm-svn: 128236
* Add support to the ARM asm parser for the register-shifted-register forms of ↵Owen Anderson2011-03-181-0/+2
| | | | | | basic instructions like ADD. More work left to be done to support other instances of shifter ops in the ISA. llvm-svn: 127917
* Add assembly parsing support for "msr" and also fix its encoding. Also addBruno Cardoso Lopes2011-02-181-0/+36
| | | | | | testcases for the disassembler to make sure it still works for "msr". llvm-svn: 125948
* Fix encoding and add parsing support for the arm/thumb CPS instruction:Bruno Cardoso Lopes2011-02-141-0/+9
| | | | | | | | | | | | - Add custom operand matching for imod and iflags. - Rename SplitMnemonicAndCC to SplitMnemonic since it splits more than CC from mnemonic. - While adding ".w" as an operand, don't change "Head" to avoid passing the wrong mnemonic to ParseOperand. - Add asm parser tests. - Add disassembler tests just to make sure it can catch all cps versions. llvm-svn: 125489
* Add support for parsing dmb/dsb instructionsBruno Cardoso Lopes2011-02-071-0/+49
| | | | llvm-svn: 125055
* fix the encoding and add testcases for ARM nop, yield, wfe and wfi instructionsBruno Cardoso Lopes2011-01-261-0/+12
| | | | llvm-svn: 124288
* Fix the encoding of QADD/SUB, QDADD/SUB. While qadd16, qadd8 use "rd, rn, rm",Bruno Cardoso Lopes2011-01-211-0/+12
| | | | | | | qadd and qdadd uses "rd, rm, rn", the same applies to the 'sub' variants. This is described in ARM manuals and matches the encoding used by the gnu assembler. llvm-svn: 123975
* Add testcases for clz encodingBruno Cardoso Lopes2011-01-201-0/+3
| | | | llvm-svn: 123937
* Fix the encoding and parsing of clrex instructionBruno Cardoso Lopes2011-01-201-0/+2
| | | | llvm-svn: 123936
* - Use a more appropriate name for Owen's ARM Parser isMCR hack since the ↵Bruno Cardoso Lopes2011-01-201-0/+5
| | | | | | | | | | same operands can be present in cdp/cdp2 instructions. Also increase the hack with cdp/cdp2 instructions. - Fix the encoding of cdp/cdp2 instructions for ARM (no thumb and thumb2 yet) and add testcases for t hem. llvm-svn: 123927
* Fix the encoding of mrrc and mcrr family of instructions. Also add testcases ↵Bruno Cardoso Lopes2011-01-191-0/+19
| | | | | | for mcr and mrc llvm-svn: 123837
* Fix MRS encoding for arm and thumb.Bruno Cardoso Lopes2011-01-181-0/+2
| | | | llvm-svn: 123778
* Fix the encoding of t2ISB by using the right class and also parse it correctlyBruno Cardoso Lopes2011-01-181-0/+3
| | | | llvm-svn: 123776
* Follow the current hack set and enable the correct parsing of bkpt while in ↵Bruno Cardoso Lopes2011-01-181-0/+3
| | | | | | thumb mode. llvm-svn: 123772
* Add support for parsing and encoding ARM's official syntax for the BFI ↵Bruno Cardoso Lopes2011-01-181-0/+3
| | | | | | instruction llvm-svn: 123770
* McARM: Add more hard coded logic to SplitMnemonicAndCC to also split out theDaniel Dunbar2011-01-111-9/+18
| | | | | | | | | | carry setting flag from the mnemonic. Note that this currently involves me disabling a number of working cases in arm_instructions.s, this is a hopefully short term evil which will be rapidly fixed (and greatly surpassed), assuming my current approach flies. llvm-svn: 123238
* Add some more MC tests for ARM arithmetic instructions that update or don'tKevin Enderby2010-12-151-8/+59
| | | | | | | update the condition codes. These come from my test generator and are just the ones that MC currently assembles correctly. llvm-svn: 121830
* Add support for parsing ARM arithmetic instructions that update or don't updateKevin Enderby2010-12-091-0/+9
| | | | | | | | | the condition codes. Where the ones that do have an 's' suffix and the ones that don't don't have the suffix. The trick is if MatchInstructionImpl() fails we try again after adding a CCOut operand with the correct value and removing the 's' if present. Four simple test cases added for now, lots more to come. llvm-svn: 121401
* Add encoding for ARM "trap" instruction.Bill Wendling2010-11-211-0/+4
| | | | llvm-svn: 119938
* Add support for parsing the writeback ("!") token.Bill Wendling2010-11-181-0/+18
| | | | llvm-svn: 119761
* Test encodings for LDM and STM.Bill Wendling2010-11-161-0/+18
| | | | llvm-svn: 119315
OpenPOWER on IntegriCloud