| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | [ARM] Add missing Thumb2 assembler diagnostics. | Eli Friedman | 2018-06-28 | 1 | -12/+12 |
| | | | | | | | | | | | Mostly just adding checks for Thumb2 instructions which correspond to ARM instructions which already had diagnostics. While I'm here, also fix ARM-mode strd to check the input registers correctly. Differential Revision: https://reviews.llvm.org/D48610 llvm-svn: 335909 | ||||
| * | ARM IAS: support GNU extension for ldrd, strd | Saleem Abdulrasool | 2014-01-10 | 1 | -0/+11 |
| | | | | | | | | | | The GNU assembler has an extension that allows for the elision of the paired register (dt2) for the LDRD and STRD mnemonics. Add support for this in the assembly parser. Canonicalise the usage during the instruction parsing from the specified version. llvm-svn: 198915 | ||||
| * | ARM: Teach assembler to enforce constraints for ARM LDRD destination ↵ | Tilmann Scheller | 2013-09-27 | 1 | -20/+20 |
| | | | | | | | | | | | | | | | | | | | | register operands. As specified in A8.8.72/A8.8.73/A8.8.74 in the ARM ARM, all variants of the ARM LDRD instruction have the following two constraints: LDRD<c> <Rt>, <Rt2>, ... (a) Rt must be even-numbered and not r14 (b) Rt2 must be R(t+1) If those two constraints are not met the result of executing the instruction will be unpredictable. Constraint (b) was already enforced, this commit adds support for constraint (a). Fixes rdar://14479793. llvm-svn: 191520 | ||||
| * | It adds support for negative zero offsets for loads and stores. | Mihai Popa | 2013-06-11 | 1 | -1/+4 |
| | | | | | | | | Negative zero is returned by the primary expression parser as INT32_MIN, so all that the method needs to do is to accept this value. Behavior already present for Thumb2. llvm-svn: 183734 | ||||
| * | ARM assembly parsing and encoding support for LDRD(label). | Jim Grosbach | 2011-12-19 | 1 | -1/+6 |
| | | | | | | | rdar://9932658 llvm-svn: 146921 | ||||
| * | ARM load shifted register pre-index fix shift value asm parser encoding. | Jim Grosbach | 2011-08-11 | 1 | -0/+2 |
| | | | | | llvm-svn: 137367 | ||||
| * | ARM STRHT assembly parsing and encoding. | Jim Grosbach | 2011-08-11 | 1 | -0/+13 |
| | | | | | llvm-svn: 137358 | ||||
| * | ARM STRH assembly parsing and encoding. | Jim Grosbach | 2011-08-11 | 1 | -0/+34 |
| | | | | | llvm-svn: 137353 | ||||
| * | ARM STRD assembly parsing and encoding. | Jim Grosbach | 2011-08-11 | 1 | -0/+39 |
| | | | | | llvm-svn: 137342 | ||||
| * | ARM STRBT assembly parsing and encoding. | Jim Grosbach | 2011-08-11 | 1 | -0/+14 |
| | | | | | llvm-svn: 137337 | ||||
| * | Add FIXME. | Jim Grosbach | 2011-08-11 | 1 | -0/+3 |
| | | | | | llvm-svn: 137336 | ||||
| * | ARM STRB assembly parsing and encoding tests. | Jim Grosbach | 2011-08-11 | 1 | -0/+38 |
| | | | | | llvm-svn: 137335 | ||||
| * | Fix a copy/paste error so that LDRB(register) actually gets tested. | Jim Grosbach | 2011-08-11 | 1 | -17/+17 |
| | | | | | llvm-svn: 137333 | ||||
| * | ARM STR(register) assembly parsing and encoding tests. | Jim Grosbach | 2011-08-11 | 1 | -0/+27 |
| | | | | | llvm-svn: 137332 | ||||
| * | ARM STR(immediate) assembly parsing and encoding. | Jim Grosbach | 2011-08-11 | 1 | -0/+14 |
| | | | | | llvm-svn: 137331 | ||||
| * | ARM tests for LDRSHT assembly parsing and encoding. | Jim Grosbach | 2011-08-10 | 1 | -0/+15 |
| | | | | | llvm-svn: 137274 | ||||
| * | ARM tests for LDRSH assembly parsing and encoding. | Jim Grosbach | 2011-08-10 | 1 | -0/+36 |
| | | | | | llvm-svn: 137272 | ||||
| * | ARM tests for LDRSBT assembly parsing and encoding. | Jim Grosbach | 2011-08-10 | 1 | -0/+12 |
| | | | | | llvm-svn: 137271 | ||||
| * | ARM tests for LDRSB assembly parsing and encoding. | Jim Grosbach | 2011-08-10 | 1 | -0/+36 |
| | | | | | llvm-svn: 137270 | ||||
| * | Add FIXME. | Jim Grosbach | 2011-08-10 | 1 | -0/+5 |
| | | | | | llvm-svn: 137265 | ||||
| * | ARM tests for LDRHT assembly parsing and encoding. | Jim Grosbach | 2011-08-10 | 1 | -0/+14 |
| | | | | | llvm-svn: 137263 | ||||
| * | ARM tests for LDRH(register) assembly parsing and encoding. | Jim Grosbach | 2011-08-10 | 1 | -0/+16 |
| | | | | | llvm-svn: 137261 | ||||
| * | ARM LDRH(immediate) assembly parsing and encoding support. | Jim Grosbach | 2011-08-10 | 1 | -4/+20 |
| | | | | | llvm-svn: 137260 | ||||
| * | Add FIXME | Jim Grosbach | 2011-08-10 | 1 | -0/+4 |
| | | | | | llvm-svn: 137258 | ||||
| * | ARM LDRD(register) assembly parsing and encoding. | Jim Grosbach | 2011-08-10 | 1 | -0/+20 |
| | | | | | | | Add support for literal encoding of #-0 along the way. llvm-svn: 137254 | ||||
| * | ARM LDRD(immediate) assembly parsing and encoding support. | Jim Grosbach | 2011-08-10 | 1 | -0/+14 |
| | | | | | llvm-svn: 137244 | ||||
| * | ARM parsing and encoding for LDRBT instruction. | Jim Grosbach | 2011-08-08 | 1 | -0/+16 |
| | | | | | | | | Fix the instruction representation to correctly only allow post-indexed form. Add tests. llvm-svn: 137074 | ||||
| * | ARM parsing and encoding for LDRB instruction. | Jim Grosbach | 2011-08-08 | 1 | -0/+38 |
| | | | | | llvm-svn: 137071 | ||||
| * | Add FIXME. | Jim Grosbach | 2011-08-08 | 1 | -0/+7 |
| | | | | | llvm-svn: 137070 | ||||
| * | ARM load instruction shifted register index operands. | Jim Grosbach | 2011-08-05 | 1 | -0/+4 |
| | | | | | | | Parsing and encoding for shifted index operands for load instructions. llvm-svn: 136986 | ||||
| * | ARM indexed load assembly parsing and encoding. | Jim Grosbach | 2011-08-05 | 1 | -0/+16 |
| | | | | | | | | More parsing support for indexed loads. Fix pre-indexed with writeback parsing for register offsets and handle basic post-indexed offsets. llvm-svn: 136982 | ||||
| * | Add ARM LDR parsing tests. | Jim Grosbach | 2011-08-05 | 1 | -0/+26 |
| llvm-svn: 136977 | |||||
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| Project Ortega BCM5719 LLVM | Raptor Computing Systems |
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