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* AMDGPU : Fix ISA Version Definitions.Wei Ding2017-06-101-2/+2
| | | | | | Differential Revision: http://reviews.llvm.org/D28531 llvm-svn: 305137
* [AMDGPU][MC] Corrected error message for s_waitcnt helpersDmitry Preobrazhensky2017-06-071-4/+4
| | | | | | | | | | See Bug 32711: https://bugs.llvm.org//show_bug.cgi?id=32711 Reviewers: artem.tamazov Differential Revision: https://reviews.llvm.org/D33781 llvm-svn: 304922
* [AMDGPU][MC] New syntax for ds_swizzle_b32 offsetDmitry Preobrazhensky2017-05-312-4/+230
| | | | | | | | | | See Bug 28601: https://bugs.llvm.org//show_bug.cgi?id=28601 Reviewers: artem.tamazov, vpykhtin Differential Revision: https://reviews.llvm.org/D33542 llvm-svn: 304309
* [AMDGPU][MC][GFX9] Corrected encoding of flat_scratch* for SDWA opcodesDmitry Preobrazhensky2017-05-261-0/+4
| | | | | | | | | | See bug 33171: https://bugs.llvm.org/show_bug.cgi?id=33171 Reviewers: Sam Kolton Differential Revision: https://reviews.llvm.org/D33553 llvm-svn: 304015
* [AMDGPU] SDWA: Add assembler support for GFX9Sam Kolton2017-05-231-169/+268
| | | | | | | | | | | | | | | Summary: Added separate pseudo and real instruction for GFX9 SDWA instructions. Currently supports only in assembler. Depends D32493 Reviewers: vpykhtin, artem.tamazov Subscribers: arsenm, kzhuravl, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye Differential Revision: https://reviews.llvm.org/D33132 llvm-svn: 303620
* [AMDGPU][MC] Fixed bugs in export instructionDmitry Preobrazhensky2017-05-191-0/+12
| | | | | | | | | | | | See Bugs 33019, 33056: https://bugs.llvm.org//show_bug.cgi?id=33019 https://bugs.llvm.org//show_bug.cgi?id=33056 Reviewers: artem.tamazov, vpykhtin Differential Revision: https://reviews.llvm.org/D33288 llvm-svn: 303423
* AMDGPU: Fix min3/max3 combines for f16/i16Matt Arsenault2017-05-171-0/+24
| | | | | | Fix missing instruction definitions for min3/max3. llvm-svn: 303284
* [AMDGPU][MC] Corrected several VI opcodes to avoid printing _e64Dmitry Preobrazhensky2017-05-152-18/+18
| | | | | | | | | | See bug 32936: https://bugs.llvm.org//show_bug.cgi?id=32936 Reviewers: artem.tamazov, vpykhtin Differential Revision: https://reviews.llvm.org/D33123 llvm-svn: 303070
* AMDGPU: Remove tfe bit from flat instruction definitionsMatt Arsenault2017-05-111-66/+0
| | | | | | | | | | We don't use it and it was removed in gfx9, and the encoding bit repurposed. Additionally actually using it requires changing the output register class, which wasn't done anyway. llvm-svn: 302814
* [AMDGPU][MC] Corrected v_madak/madmk to avoid printing "_e32" in ↵Dmitry Preobrazhensky2017-05-102-12/+12
| | | | | | | | | | | | disassembler output See bug 32927: https://bugs.llvm.org//show_bug.cgi?id=32927 Reviewers: vpykhtin, artem.tamazov, arsenm Differential Revision: https://reviews.llvm.org/D32913 llvm-svn: 302648
* [AMDGPU] DPP: add support for GFX9Sam Kolton2017-04-272-138/+147
| | | | | | | | | | Reviewers: artem.tamazov Subscribers: arsenm, kzhuravl, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye Differential Revision: https://reviews.llvm.org/D32588 llvm-svn: 301551
* [AMDGPU][MC] Added arg checks for vmcnt, expcnt, lgkmcnt helpersDmitry Preobrazhensky2017-04-262-0/+56
| | | | | | | | | | | | | | Summary of changes: - corrected vmcnt, expcnt, lgkmcnt helpers to checks their argument for truncation; - added saturated versions of these helpers. See bug 32711 for details: https://bugs.llvm.org//show_bug.cgi?id=32711 Reviewers: artem.tamazov, vpykhtin Differential Revision: https://reviews.llvm.org/D32546 llvm-svn: 301439
* [AMDGPU][MC] Added check for truncation of SOPK imm operandDmitry Preobrazhensky2017-04-262-0/+27
| | | | | | | | | | See bug 30827: https://bugs.llvm.org//show_bug.cgi?id=30827 Reviewers: artem.tamazov, vpykhtin Differential Revision: https://reviews.llvm.org/D32535 llvm-svn: 301418
* [AMDGPU][mc][tests][NFC] Bulk ISA tests: update for Gfx7/Gfx8, add for Gfx9.Artem Tamazov2017-04-243-251/+63301
| | | | llvm-svn: 301247
* [AMDGPU][mc][tests][NFC] Update bulk ISA tests for Gfx7 and Gfx8Artem Tamazov2017-04-192-4377/+10806
| | | | | | Added approx. 1100 gfx7 and 1040 gfx8 test cases. llvm-svn: 300734
* [AMDGPU][MC] Corrected ds_write_src2_* to require one offset instead of two.Dmitry Preobrazhensky2017-04-141-6/+6
| | | | | | | | | | Fixed bug 32551: https://bugs.llvm.org//show_bug.cgi?id=32551 Reviewers: vpykhtin Differential Revision: https://reviews.llvm.org/D31809 llvm-svn: 300319
* [AMDGPU][MC] Enabled constants for src operands of s_cbranch_g_forkDmitry Preobrazhensky2017-04-142-0/+15
| | | | | | | | | | Fixed bug 32619: https://bugs.llvm.org//show_bug.cgi?id=32619 Reviewers: artem.tamazov, vpykhtin Differential Revision: https://reviews.llvm.org/D31973 llvm-svn: 300318
* [AMDGPU][MC] Added support for several VI-specific opcodes (s_wakeup, etc)Dmitry Preobrazhensky2017-04-123-1/+23
| | | | | | | | | | | | | | | | | | | | | | Added support for VI: - s_endpgm_saved - s_wakeup - s_rfe_restore_b64 - v_perm_b32 Enabled for VI: - v_mov_fed_b32 - v_mov_fed_b32_e64 See bug 32593: https://bugs.llvm.org//show_bug.cgi?id=32593 Reviewers: artem.tamazov, vpykhtin Differential Revision: https://reviews.llvm.org/D31931 llvm-svn: 300076
* [AMDGPU][MC] Corrected parsing of v_cmp_class* and v_cmpx_class*Dmitry Preobrazhensky2017-04-121-0/+24
| | | | | | | | | | Fixed bug 32565: https://bugs.llvm.org//show_bug.cgi?id=32565 Reviewers: vpykhtin Differential Revision: https://reviews.llvm.org/D31820 llvm-svn: 300073
* [AMDGPU][MC] Corrected encoding of V_MQSAD_U32_U8 for CIDmitry Preobrazhensky2017-04-121-1/+1
| | | | | | | | | | | | Corrected encoding of V_MQSAD_U32_U8 for CI See bug 32552: https://bugs.llvm.org//show_bug.cgi?id=32552 Reviewers: vpykhtin Differential Revision: https://reviews.llvm.org/D31810 llvm-svn: 300070
* [AMDGPU][MC] Corrected ds_wrxchg2* to support two offsetsDmitry Preobrazhensky2017-04-121-0/+16
| | | | | | | | | | Fixed bug 28227: https://bugs.llvm.org//show_bug.cgi?id=28227 Reviewers: vpykhtin Differential Revision: https://reviews.llvm.org/D31808 llvm-svn: 300066
* [AMDGPU][MC] Corrected src0 size for s_cbranch_joinDmitry Preobrazhensky2017-04-121-3/+11
| | | | | | | | | | Fix for bug 28159: https://bugs.llvm.org//show_bug.cgi?id=28159 Reviewers: vpykhtin, arsenm Differential Revision: https://reviews.llvm.org/D31595 llvm-svn: 300055
* [AMDGPU][MC] Fix for Bug 28211 + LIT testsDmitry Preobrazhensky2017-04-074-29/+145
| | | | | | | | | | | | | | | | | | | | - corrected DS_GWS_* opcodes (see VI_Shader_Programming#16.pdf for detailed description) - address operand is not used - several opcodes have data operand - all opcodes have offset modifier - DS_AND_SRC2_B32: corrected typo in mnemo - DS_WRAP_RTN_F32 replaced with DS_WRAP_RTN_B32 - added CI/VI opcodes: - DS_CONDXCHG32_RTN_B64 - DS_GWS_SEMA_RELEASE_ALL - added VI opcodes: - DS_CONSUME - DS_APPEND - DS_ORDERED_COUNT Differential Revision: https://reviews.llvm.org/D31707 llvm-svn: 299767
* [AMDGPU][MC] Fix for Bug 28158 + LIT testsDmitry Preobrazhensky2017-04-051-0/+15
| | | | | | | | | | | | | | | Added support of the following instructions: - s_cbranch_cdbgsys - s_cbranch_cdbgsys_and_user - s_cbranch_cdbgsys_or_user - s_cbranch_cdbguser - s_setkill Reviewers: vpykhtin Differential Revision: https://reviews.llvm.org/D31469 llvm-svn: 299567
* [AMDGPU][MC] Fix for Bug 28167 + LIT testsDmitry Preobrazhensky2017-04-051-0/+8
| | | | | | | | | | | | Corrected src0 for v_writelane_b32: - Enabled inline constants and literals for SI/CI (VOP2) - Enabled inline constants for VI (VOP3) Reviewers: vpykhtin, arsenm https://reviews.llvm.org/D31463 llvm-svn: 299555
* [AMDGPU][MC] Fix for Bug 28207 + LIT testsDmitry Preobrazhensky2017-03-271-1/+131
| | | | | | | | | | Enabled clamp and omod for v_cvt_* opcodes which have src0 of an integer type Reviewers: vpykhtin, arsenm Differential Revision: https://reviews.llvm.org/D31327 llvm-svn: 298852
* [AMDGPU] Rename Kind to ValueKind in metadata to be consistentKonstantin Zhuravlyov2017-03-242-15/+15
| | | | llvm-svn: 298722
* [AMDGPU] Do not emit isa info as code object metadataKonstantin Zhuravlyov2017-03-224-146/+0
| | | | | | | | - It was decided to expose this information through other means (rocr) Differential Revision: https://reviews.llvm.org/D30970 llvm-svn: 298560
* [AMDGPU] Emit kernel debug properties as code object metadataKonstantin Zhuravlyov2017-03-222-4/+30
| | | | | | Differential Revision: https://reviews.llvm.org/D30969 llvm-svn: 298558
* [AMDGPU] Emit kernel code properties as code object metadataKonstantin Zhuravlyov2017-03-221-0/+24
| | | | | | | | - These are not required for low level runtime Differential Revision: https://reviews.llvm.org/D29949 llvm-svn: 298556
* [AMDGPU] Restructure code object metadata creationKonstantin Zhuravlyov2017-03-228-202/+295
| | | | | | | | | | | | | | | | | - Rename runtime metadata -> code object metadata - Make metadata not flow - Switch enums to use ScalarEnumerationTraits - Cleanup and move AMDGPUCodeObjectMetadata.h to AMDGPU/MCTargetDesc - Introduce in-memory representation for attributes - Code object metadata streamer - Create metadata for isa and printf during EmitStartOfAsmFile - Create metadata for kernel during EmitFunctionBodyStart - Finalize and emit metadata to .note during EmitEndOfAsmFile - Other minor improvements/bug fixes Differential Revision: https://reviews.llvm.org/D29948 llvm-svn: 298552
* [AMDGPU][MC] Fix for Bug 28204 + LIT testsDmitry Preobrazhensky2017-03-221-0/+10
| | | | | | | | | | Fixed v_mad_i64_i32/u64_u32 encoding Reviewers: artem.tamazov Differential Revision: https://reviews.llvm.org/D30828 llvm-svn: 298502
* [AMDGPU][MC] Fix for Bugs 28201, 28199, 28170 + LIT testsDmitry Preobrazhensky2017-03-201-0/+12
| | | | | | | | | | This fix enables sp3 abs modifier with constants Reviewers: artem.tamazov Differential Revision: https://reviews.llvm.org/D30825 llvm-svn: 298265
* [AMDGPU][MC] Fix for Bugs 28200, 28202 + LIT testsDmitry Preobrazhensky2017-03-204-6/+279
| | | | | | | | | | Fixed several related issues with VOP3 fp modifiers. Reviewers: artem.tamazov Differential Revision: https://reviews.llvm.org/D30821 llvm-svn: 298255
* [AMDGPU][MC] Fix for Bug 30829 + LIT testsDmitry Preobrazhensky2017-03-032-0/+297
| | | | | | | | Added code to check constant bus restrictions for VOP formats (only one SGPR value or literal-constant may be used by the instruction). Note that the same checks are performed by SIInstrInfo::verifyInstruction (used by lowering code). Added LIT tests. llvm-svn: 296873
* AMDGPU: Add definition for v_swap_b32Matt Arsenault2017-02-282-0/+38
| | | | | | | | This is somewhat tricky because there are two pairs of tied operands, and it isn't allowed to be VOP3 encoded. llvm-svn: 296519
* AMDGPU: Add definition for v_xad_u32Matt Arsenault2017-02-281-0/+4
| | | | llvm-svn: 296515
* AMDGPU: Add ds_nop to assemblerMatt Arsenault2017-02-281-0/+5
| | | | llvm-svn: 296513
* AMDGPU: Add definitions for ds_{read|write}_b{96|128}Matt Arsenault2017-02-281-0/+9
| | | | | | | | | It's not clear to me if this is always better than doing ds_write2_b64 This adds the constraint of a 128-bit register input instead of a pair of 64-bit. llvm-svn: 296512
* [AMDGPU] Change amd_kernel_code_t's minor version to 1Konstantin Zhuravlyov2017-02-282-2/+2
| | | | | | | | - We do emit amd_kernel_code_t v1.1 Differential Revision: https://reviews.llvm.org/D30433 llvm-svn: 296489
* AMDGPU: Use v_med3_{f16|i16|u16}Matt Arsenault2017-02-271-0/+12
| | | | llvm-svn: 296401
* AMDGPU: Add some of the new gfx9 VOP3 instructionsMatt Arsenault2017-02-271-0/+32
| | | | llvm-svn: 296382
* AMDGPU: Add VOP3P instruction formatMatt Arsenault2017-02-274-0/+463
| | | | | | | | Add a few non-VOP3P but instructions related to packed. Includes hack with dummy operands for the benefit of the assembler llvm-svn: 296368
* [AMDGPU] Runtime metadata fixes:Konstantin Zhuravlyov2017-02-275-42/+191
| | | | | | | | | | | - Verify that runtime metadata is actually valid runtime metadata when assembling, otherwise we could accept the following when assembling, but ocl runtime will reject it: .amdgpu_runtime_metadata { amd.MDVersion: [ 2, 1 ], amd.RandomUnknownKey, amd.IsaInfo: ... - Make IsaInfo optional, and always emit it. Differential Revision: https://reviews.llvm.org/D30349 llvm-svn: 296324
* * [AMDGPU][mc][tests] Updated coverage/smoke tests for gfx7 and gfx8; minor ↵Dmitry Preobrazhensky2017-02-224-100835/+114665
| | | | | | | test corrections. NB: several old tests have been corrected because they violated constant bus limitations llvm-svn: 295834
* Test commitDmitry Preobrazhensky2017-02-212-0/+4
| | | | llvm-svn: 295740
* AMDGPU: Merge initial gfx9 supportMatt Arsenault2017-02-181-0/+71
| | | | llvm-svn: 295554
* [AMDGPU][mc][tests][NFC] Add coverage/smoke Gfx7 asm test (3rd attempt)Artem Tamazov2017-02-031-0/+63289
| | | | llvm-svn: 294047
* AMDGPU: Use source modifiers with f16->f32 conversionsMatt Arsenault2017-02-021-2/+4
| | | | | | | | | | | The operand types were defined to fit the fp16_to_fp node, which has the half as an integer type. v_cvt_f32_f16 does support source modifiers, so change this to have an FP type and modifiers. For targets without legal f16, this requires recognizing the bit operations and trying to produce them. llvm-svn: 293857
* [AMDGPU][mc][tests][NFC] Revert coverage/smoke Gfx7 asm testArtem Tamazov2017-01-311-63301/+0
| | | | | | | | Reason: http://lab.llvm.org:8080/green/job/clang-stage2-cmake-RgSan_check/2916/testReport/junit/LLVM/MC_AMDGPU/gfx7_asm_all_s/ This seems to reveal an AMDGPU/mc issue which needs to be triaged & fixed prior re-committing the test. llvm-svn: 293642
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