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* [AMDGPU][MC][GFX8][GFX9] Added XNACK_MASK supportDmitry Preobrazhensky2018-01-101-0/+30
| | | | | | | | | See bug 35764: https://bugs.llvm.org/show_bug.cgi?id=35764 Differential Revision: https://reviews.llvm.org/D41614 Reviewers: vpykhtin, artem.tamazov, arsenm llvm-svn: 322189
* [AMDGPU][MC] Incorrect parsing of flat/global atomic modifiersDmitry Preobrazhensky2017-12-291-0/+48
| | | | | | | | | See bug 35730: https://bugs.llvm.org/show_bug.cgi?id=35730 Differential Revision: https://reviews.llvm.org/D41598 Reviewers: vpykhtin, artem.tamazov, arsenm llvm-svn: 321552
* [AMDGPU][MC] Corrected handling of negative expressionsDmitry Preobrazhensky2017-12-222-3/+11
| | | | | | | | | | See bug 35716: https://bugs.llvm.org/show_bug.cgi?id=35716 Reviewers: artem.tamazov, arsenm Differential Revision: https://reviews.llvm.org/D41488 llvm-svn: 321372
* [AMDGPU][MC] Corrected parsing of optional operands for ds_swizzle_b32Dmitry Preobrazhensky2017-12-221-0/+4
| | | | | | | | | | See bug 35645: https://bugs.llvm.org/show_bug.cgi?id=35645 Reviewers: artem.tamazov, arsenm Differential Revision: https://reviews.llvm.org/D41186 llvm-svn: 321367
* [AMDGPU][MC] Added support of 256- and 512-bit tuples of ttmp registersDmitry Preobrazhensky2017-12-221-0/+42
| | | | | | | | | | | | See bug 35561: https://bugs.llvm.org/show_bug.cgi?id=35561 This patch also affects implementation of SGPR and VGPR registers though changes are cosmetic. Reviewers: artem.tamazov, arsenm Differential Revision: https://reviews.llvm.org/D41437 llvm-svn: 321359
* [AMDGPU, AsmParser] Enable the mnemonic spell corrector.Matt Arsenault2017-12-202-5/+55
| | | | | | Patch by Dmitry Venikov llvm-svn: 321202
* [AMDGPU][MC][GFX9] Corrected encoding of ttmp registers, disabled tba/tmaDmitry Preobrazhensky2017-12-114-8/+114
| | | | | | | | | | | | See bugs 35494 and 35559: https://bugs.llvm.org/show_bug.cgi?id=35494 https://bugs.llvm.org/show_bug.cgi?id=35559 Reviewers: vpykhtin, artem.tamazov, arsenm Differential Revision: https://reviews.llvm.org/D41007 llvm-svn: 320375
* AMDGPU/GCN: Bring processors in sync with AMDGPUUsageKonstantin Zhuravlyov2017-12-088-16/+12
| | | | | | | | | | | | - Add gfx704 - Change bonaire to gfx704 - Remove gfx804 - Remove gfx901 - Remove gfx903 Differential Revision: https://reviews.llvm.org/D40046 llvm-svn: 320194
* AMDGPU: Add num spilled s/vgprs to metadataKonstantin Zhuravlyov2017-11-281-0/+4
| | | | | | | | This was requested by tools. Differential Revision: https://reviews.llvm.org/D40321 llvm-svn: 319192
* [AMDGPU][MC][GFX9] Added v_interp_p2_f16 and v_interp_p2_legacy_f16Dmitry Preobrazhensky2017-11-241-0/+36
| | | | | | | | | | See bug 33629: https://bugs.llvm.org//show_bug.cgi?id=33629 Reviewers: artem.tamazov, SamWot, arsenm Differential Revision: https://reviews.llvm.org/D39488 llvm-svn: 318955
* [AMDGPU][MC][GFX9] Added support of 'inst_offset' modifier for compatibility ↵Dmitry Preobrazhensky2017-11-241-0/+4
| | | | | | | | | | | | with SP3 See bug 35329: https://bugs.llvm.org//show_bug.cgi?id=35329 Reviewers: arsenm, vpykhtin, artem.tamazov Differential Revision: https://reviews.llvm.org/D40350 llvm-svn: 318947
* [AMDGPU][mc][tests] Updated generated lit tests for GFX8/9Dmitry Preobrazhensky2017-11-222-0/+5112
| | | | | | | | Summary: Added tests to better cover features introduced by commit rL318675. See http://llvm.org/viewvc/llvm-project?view=revision&revision=318675 llvm-svn: 318841
* [AMDGPU][MC][GFX8][GFX9] Corrected names of integer ↵Dmitry Preobrazhensky2017-11-205-89/+143
| | | | | | | | | | | | v_{add/addc/sub/subrev/subb/subbrev} See bug 34765: https://bugs.llvm.org//show_bug.cgi?id=34765 Reviewers: tamazov, SamWot, arsenm, vpykhtin Differential Revision: https://reviews.llvm.org/D40088 llvm-svn: 318675
* [AMDGPU][MC][GFX9][disassembler] Corrected decoding of op_sel_hi for v_mad_mix*Dmitry Preobrazhensky2017-11-171-23/+23
| | | | | | | | | | See bug 35148: https://bugs.llvm.org//show_bug.cgi?id=35148 Reviewers: tamazov, SamWot, arsenm Differential Revision: https://reviews.llvm.org/D39492 llvm-svn: 318526
* AMDGPU: Rename MaxFlatWorkgroupSize to MaxFlatWorkGroupSize for consistencyKonstantin Zhuravlyov2017-10-181-2/+2
| | | | | | Differential Revision: https://reviews.llvm.org/D38957 llvm-svn: 316097
* AMDGPU: Start generating metadata for MaxFlatWorkGroupSizeKonstantin Zhuravlyov2017-10-171-0/+2
| | | | | | Differential Revision: https://reviews.llvm.org/D38958 llvm-svn: 316024
* AMDGPU: Bring HSA metadata on par with the specificationKonstantin Zhuravlyov2017-10-146-18/+33
| | | | | | Differential Revision: https://reviews.llvm.org/D38753 llvm-svn: 315821
* AMDGPU: Improve note directive verification in assemblerKonstantin Zhuravlyov2017-10-142-0/+17
| | | | | | | | | | - Do not allow amd_amdgpu_isa directives on non-amdgcn architectures - Do not allow amd_amdgpu_hsa_metadata on non-amdhsa OSes - Do not allow amd_amdgpu_pal_metadata on non-amdpal OSes Differential Revision: https://reviews.llvm.org/D38750 llvm-svn: 315812
* AMDGPU: Do not emit deprecated notes for code object v3Konstantin Zhuravlyov2017-10-142-2/+0
| | | | | | Differential Revision: https://reviews.llvm.org/D38749 llvm-svn: 315810
* AMDGPU: Add support for isa version noteKonstantin Zhuravlyov2017-10-143-0/+41
| | | | | | | | | | - Emit NT_AMD_AMDGPU_ISA - Add assembler parsing for isa version directive - If isa version directive does not match command line arguments, then return error Differential Revision: https://reviews.llvm.org/D38748 llvm-svn: 315808
* AMDGPU/NFC: Minor clean ups in PAL metadataKonstantin Zhuravlyov2017-10-111-2/+2
| | | | | | | | | - Move PAL metadata definitions to AMDGPUMetadata - Make naming consistent with HSA metadata Differential Revision: https://reviews.llvm.org/D38745 llvm-svn: 315523
* AMDGPU/NFC: Rename code object metadata as HSA metadataKonstantin Zhuravlyov2017-10-116-20/+20
| | | | | | | | | - Rename AMDGPUCodeObjectMetadata to AMDGPUMetadata (PAL metadata will be included in this file in the follow up change) - Rename AMDGPUCodeObjectMetadataStreamer to AMDGPUHSAMetadataStreamer - Introduce HSAMD namespace - Other minor name changes in function and test names llvm-svn: 315522
* [AMDGPU] implemented pal metadataTim Renouf2017-10-031-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: For the amdpal OS type: We write an AMDGPU_PAL_METADATA record in the .note section in the ELF (or as an assembler directive). It contains key=value pairs of 32 bit ints. It is a merge of metadata from codegen of the shaders, and metadata provided by the frontend as _amdgpu_pal_metadata IR metadata. Where both sources have a key=value with the same key, the two values are ORed together. This .note record is part of the amdpal ABI and will be documented in docs/AMDGPUUsage.rst in a future commit. Eventually the amdpal OS type will stop generating the .AMDGPU.config section once the frontend has safely moved over to using the .note records above instead of .AMDGPU.config. Reviewers: arsenm, nhaehnle, dstuttard Subscribers: kzhuravl, wdng, yaxunl, llvm-commits, t-tye Differential Revision: https://reviews.llvm.org/D37753 llvm-svn: 314829
* AMDGPU: fix bad test exposed by r314522Nicolai Haehnle2017-09-291-8/+0
| | | | | | | | | | | The test attempts to use -1 as carry-in for v_addc_*. Before writing r314522, I did actually test this on real hardware, and found that it doesn't work. So r314522 is correct in restricting the carry-in operand: just remove those tests to make things pass again. llvm-svn: 314530
* AMDGPU: Fix encoding of op_sel for mad_mix* opcodesMatt Arsenault2017-09-201-10/+10
| | | | llvm-svn: 313797
* AMDGPU: Add ds_{read|write}_addtid_b32 definitionsMatt Arsenault2017-09-011-0/+8
| | | | llvm-svn: 312349
* AMDGPU: Add most d16 load/store instruction definitionsMatt Arsenault2017-09-015-0/+164
| | | | | | | Doesn't include the tied operand necessary for the loads, but is enough for the assembler to work. llvm-svn: 312347
* AMDGPU: Correct operand types for v_mad_mix*Matt Arsenault2017-08-302-482/+35
| | | | | | | | | | | | These aren't really packed instructions, so the default op_sel_hi should be 0 since this indicates a conversion. The operand types are scalar values that behave similar to an f16 scalar that may be converted to f32. Doesn't change the default printing for op_sel_hi, just the parsing. llvm-svn: 312179
* [AMDGPU][MC][GFX9] Added op_sel support for v_mad_*16, v_fma_f16, ↵Dmitry Preobrazhensky2017-08-161-0/+51
| | | | | | | | | | | | v_div_fixup_f16 This change implements features postponed in https://reviews.llvm.org/D35424 because of a dependency on https://reviews.llvm.org/D36322 Reviewers: SamWot, artem.tamazov, arsenm Differential Revision: https://reviews.llvm.org/D36694 llvm-svn: 311011
* [AMDGPU][MC][GFX9] Added integer clamping support for VOP3 opcodesDmitry Preobrazhensky2017-08-162-0/+64
| | | | | | | | | | See Bug 34152: https://bugs.llvm.org//show_bug.cgi?id=34152 Reviewers: SamWot, artem.tamazov, arsenm Differential Revision: https://reviews.llvm.org/D36674 llvm-svn: 311006
* [AMDGPU][MC][GFX9] Added 16-bit renamed and "_legacy" VALU opcodesDmitry Preobrazhensky2017-08-092-0/+214
| | | | | | | | | | See Bug 33629: https://bugs.llvm.org//show_bug.cgi?id=33629 Reviewers: vpykhtin, SamWot, arsenm Differential Revision: https://reviews.llvm.org/D36322 llvm-svn: 310497
* AMDGPU: Remove -mcpu=SIMatt Arsenault2017-08-0723-28/+28
| | | | | | Leftover from before amdgcn/r600 split. llvm-svn: 310277
* [AMDGPU][MC] Corrected VOP3 version of v_interp_* instructions for VIDmitry Preobrazhensky2017-08-072-1/+238
| | | | | | | | | | See bug 32621: https://bugs.llvm.org//show_bug.cgi?id=32621 Reviewers: vpykhtin, SamWot, arsenm Differential Revision: https://reviews.llvm.org/D35902 llvm-svn: 310251
* [AMDGPU][MC] Enabled expressions as operandsDmitry Preobrazhensky2017-08-042-3/+10
| | | | | | | | | | See bug 33579: https://bugs.llvm.org//show_bug.cgi?id=33579 Reviewers: vpykhtin, SamWot, arsenm Differential Revision: https://reviews.llvm.org/D36091 llvm-svn: 310059
* AMDGPU: Add instruction definitions for some scratch_* instructionsMatt Arsenault2017-07-211-0/+145
| | | | | | Omit atomics for now since they probably aren't useful. llvm-svn: 308747
* [AMDGPU][MC][GFX9] Added support of VOP3 'op_sel' modifierDmitry Preobrazhensky2017-07-213-1034/+2462
| | | | | | | | | | See bug 33591: https://bugs.llvm.org//show_bug.cgi?id=33591 Reviewers: vpykhtin, artem.tamazov, SamWot, arsenm Differential Revision: https://reviews.llvm.org/D35424 llvm-svn: 308740
* AMDGPU: Add encoding for carryless add/sub instructionsMatt Arsenault2017-07-201-0/+104
| | | | llvm-svn: 308639
* AMDGPU: Add encodings for global atomicsMatt Arsenault2017-07-201-0/+209
| | | | llvm-svn: 308638
* AMDGPU: Correct encoding for global instructionsMatt Arsenault2017-07-202-49/+110
| | | | | | | | | | | | | | The soffset field needs to be be set to 0x7f to disable it, not 0. 0 is interpreted as an SGPR offset. This should be enough to get basic usage of the global instructions working. Technically it is possible to use an SGPR_32 offset, but I'm not sure if it's correct with 64-bit pointers, but that is not handled now. This should also be cleaned up to be more similar to how different MUBUF modes are handled, and to have InstrMappings between the different types. llvm-svn: 308583
* [AMDGPU] resubmit r308179: CodeGen: check dst operand type to determine if ↵Sam Kolton2017-07-181-13/+25
| | | | | | omod is supported for VOP3 instructions llvm-svn: 308310
* [AMDGPU][MC] Added missing VOP3P opcodesDmitry Preobrazhensky2017-07-181-0/+351
| | | | | | | | | | | | | | | Added support of the following opcodes: v_pk_sub_u16 v_pk_mad_i16 v_pk_mad_u16 See Bug 33593: https://bugs.llvm.org//show_bug.cgi?id=33593 Reviewers: vpykhtin, artem.tamazov, arsenm Differential Revision: https://reviews.llvm.org/D34890 llvm-svn: 308281
* Revert r308179 which causes tablegen to spam stderr on every build.Chandler Carruth2017-07-181-25/+13
| | | | | | | Original commit log: [AMDGPU] CodeGen: check dst operand type to determine if omod is supported for VOP3 instructions llvm-svn: 308270
* [AMDGPU] CodeGen: check dst operand type to determine if omod is supported ↵Sam Kolton2017-07-171-13/+25
| | | | | | | | | | | | | | | | for VOP3 instructions Summary: Previously, CodeGen checked first src operand type to determine if omod is supported by instruction. This isn't correct for some instructions: e.g. V_CMP_EQ_F32 has floating-point src operands but desn't support omod. Changed .td files to check if dst operand instead of src operand. Reviewers: arsenm, vpykhtin Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye Differential Revision: https://reviews.llvm.org/D35350 llvm-svn: 308179
* [AMDGPU][mc][gfx9] Added support of op_sel/op_sel_hi for V_MAD_MIX*Dmitry Preobrazhensky2017-07-073-56/+507
| | | | | | | | | | See https://bugs.llvm.org//show_bug.cgi?id=33595 Reviewers: vpykhtin, artem.tamazov, arsenm Differential Revision: https://reviews.llvm.org/D35021 llvm-svn: 307402
* Fix ODR violations due to abuse of LLVM_YAML_IS_(FLOW_)?SEQUENCE_VECTORRichard Smith2017-06-302-2/+6
| | | | | | | | | | | | | | | | | | | | | | | | This is a short-term fix for PR33650 aimed to get the modules build bots green again. Remove all the places where we use the LLVM_YAML_IS_(FLOW_)?SEQUENCE_VECTOR macros to try to locally specialize a global template for a global type. That's not how C++ works. Instead, we now centrally define how to format vectors of fundamental types and of string (std::string and StringRef). We use flow formatting for the former cases, since that's the obvious right thing to do; in the latter case, it's less clear what the right choice is, but flow formatting is really bad for some cases (due to very long strings), so we pick block formatting. (Many of the cases that were using flow formatting for strings are improved by this change.) Other than the flow -> block formatting change for some vectors of strings, this should result in no functionality change. Differential Revision: https://reviews.llvm.org/D34907 Corresponding updates to clang, clang-tools-extra, and lld to follow. llvm-svn: 306878
* [AMDGPU] Add intrinsics for tbuffer load and storeDavid Stuttard2017-06-221-0/+36
| | | | | | | | | | | | | | | Intrinsic already existed for llvm.SI.tbuffer.store Needed tbuffer.load and also re-implementing the intrinsic as llvm.amdgcn.tbuffer.* Added CodeGen tests for the 2 new variants added. Left the original llvm.SI.tbuffer.store implementation to avoid issues with existing code Subscribers: arsenm, kzhuravl, wdng, nhaehnle, yaxunl, tony-tye, tpr Differential Revision: https://reviews.llvm.org/D30687 llvm-svn: 306031
* [AMDGPU][MC] Corrected V_*QSAD* instructions to check that dest register is ↵Dmitry Preobrazhensky2017-06-213-9/+33
| | | | | | | | | | | | different than any of the src See Bug 33279: https://bugs.llvm.org//show_bug.cgi?id=33279 Reviewers: artem.tamazov, vpykhtin Differential Revision: https://reviews.llvm.org/D34003 llvm-svn: 305915
* AMDGPU: Start adding global_* instructionsMatt Arsenault2017-06-201-0/+87
| | | | llvm-svn: 305838
* [AMDGPU][mc][tests][NFC] Bulk ISA tests: Massive update. Add Gfx9 dasm tests.Artem Tamazov2017-06-193-59973/+133635
| | | | | | | | | | | A new Gfx9 dasm test added with approx 29000 cases. Existing tests extended by (approx.): * Gfx7 asm: 5000 test cases * Gfx8 asm: 5000 test cases * Gfx9 asm: 14400 test cases * Gfx8 dasm: 5200 test cases llvm-svn: 305702
* AMDGPU: Start adding offset fields to flat instructionsMatt Arsenault2017-06-122-1/+42
| | | | llvm-svn: 305194
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